From: David Gibson <david@gibson.dropbear.id.au>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org, Bin Meng <bin.meng@windriver.com>,
Eduardo Habkost <ehabkost@redhat.com>, Greg Kurz <groug@kaod.org>,
haxm-team@intel.com, Kamil Rytarowski <kamil@netbsd.org>,
qemu-ppc@nongnu.org, Anthony Perard <anthony.perard@citrix.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Michael Rolnik <mrolnik@gmail.com>,
qemu-riscv@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Thomas Huth <thuth@redhat.com>,
David Hildenbrand <david@redhat.com>,
Chris Wulff <crwulff@gmail.com>,
Laurent Vivier <lvivier@redhat.com>,
Cameron Esfahani <dirty@apple.com>,
Sunil Muthuswamy <sunilmut@microsoft.com>,
Max Filippov <jcmvbkbc@gmail.com>,
Taylor Simpson <tsimpson@quicinc.com>,
qemu-s390x@nongnu.org,
Richard Henderson <richard.henderson@linaro.org>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Yoshinori Sato <ysato@users.sourceforge.jp>,
Artyom Tarasenko <atar4qemu@gmail.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Paul Durrant <paul@xen.org>,
Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Laurent Vivier <laurent@vivier.eu>,
Cornelia Huck <cohuck@redhat.com>,
qemu-arm@nongnu.org, Wenchao Wang <wenchao.wang@intel.com>,
xen-devel@lists.xenproject.org, Marek Vasut <marex@denx.de>,
Stefano Stabellini <sstabellini@kernel.org>,
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Colin Xu <colin.xu@intel.com>, Claudio Fontana <cfontana@suse.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
Stafford Horne <shorne@gmail.com>,
Reinoud Zandijk <reinoud@netbsd.org>,
kvm@vger.kernel.org
Subject: Re: [PATCH v3 21/30] target/ppc: Introduce PowerPCCPUClass::has_work()
Date: Fri, 3 Sep 2021 10:50:45 +1000 [thread overview]
Message-ID: <YTFxZb1Vg5pWVW9p@yekko> (raw)
In-Reply-To: <20210902161543.417092-22-f4bug@amsat.org>
[-- Attachment #1: Type: text/plain, Size: 8607 bytes --]
On Thu, Sep 02, 2021 at 06:15:34PM +0200, Philippe Mathieu-Daudé wrote:
> Each POWER cpu has its own has_work() implementation. Instead of
> overloading CPUClass on each PowerPCCPUClass init, register the
> generic ppc_cpu_has_work() handler, and have it call the POWER
> specific has_work().
I don't quite see the rationale for introducing a second layer of
indirection here. What's wrong with switching the base has_work for
each cpu variant?
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/ppc/cpu-qom.h | 3 +++
> target/ppc/cpu_init.c | 26 ++++++++++++++++++--------
> 2 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 5800fa324e8..ff2bafcde6f 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -189,6 +189,9 @@ struct PowerPCCPUClass {
> int bfd_mach;
> uint32_t l1_dcache_size, l1_icache_size;
> #ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_TCG
> + bool (*has_work)(CPUState *cpu);
> +#endif /* CONFIG_TCG */
> unsigned int gdb_num_sprs;
> const char *gdb_spr_xml;
> #endif
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e2e721c2b81..bbad16cc1ec 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7583,6 +7583,7 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
> return false;
> }
>
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static bool cpu_has_work_POWER7(CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> @@ -7616,12 +7617,12 @@ static bool cpu_has_work_POWER7(CPUState *cs)
> return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> }
> }
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> - CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER7";
> dc->desc = "POWER7";
> @@ -7630,7 +7631,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER7;
> pcc->check_pow = check_pow_nocheck;
> - cc->has_work = cpu_has_work_POWER7;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -7673,6 +7673,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
> + pcc->has_work = cpu_has_work_POWER7;
> pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->lrg_decr_bits = 32;
> #endif
> @@ -7743,6 +7744,7 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
> return false;
> }
>
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static bool cpu_has_work_POWER8(CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> @@ -7784,12 +7786,12 @@ static bool cpu_has_work_POWER8(CPUState *cs)
> return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> }
> }
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> - CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER8";
> dc->desc = "POWER8";
> @@ -7798,7 +7800,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER8;
> pcc->check_pow = check_pow_nocheck;
> - cc->has_work = cpu_has_work_POWER8;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -7848,6 +7849,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> LPCR_P8_PECE3 | LPCR_P8_PECE4;
> pcc->mmu_model = POWERPC_MMU_2_07;
> #if defined(CONFIG_SOFTMMU)
> + pcc->has_work = cpu_has_work_POWER8;
> pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->lrg_decr_bits = 32;
> pcc->n_host_threads = 8;
> @@ -7941,6 +7943,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
> return false;
> }
>
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static bool cpu_has_work_POWER9(CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> @@ -7998,12 +8001,12 @@ static bool cpu_has_work_POWER9(CPUState *cs)
> return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> }
> }
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> - CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER9";
> dc->desc = "POWER9";
> @@ -8013,7 +8016,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER9;
> pcc->check_pow = check_pow_nocheck;
> - cc->has_work = cpu_has_work_POWER9;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -8062,6 +8064,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> pcc->mmu_model = POWERPC_MMU_3_00;
> #if defined(CONFIG_SOFTMMU)
> + pcc->has_work = cpu_has_work_POWER9;
> /* segment page size remain the same */
> pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->radix_page_info = &POWER9_radix_page_info;
> @@ -8150,6 +8153,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
> return false;
> }
>
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static bool cpu_has_work_POWER10(CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> @@ -8207,12 +8211,12 @@ static bool cpu_has_work_POWER10(CPUState *cs)
> return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> }
> }
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> - CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER10";
> dc->desc = "POWER10";
> @@ -8223,7 +8227,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER10;
> pcc->check_pow = check_pow_nocheck;
> - cc->has_work = cpu_has_work_POWER10;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> @@ -8275,6 +8278,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> pcc->mmu_model = POWERPC_MMU_3_00;
> #if defined(CONFIG_SOFTMMU)
> + pcc->has_work = cpu_has_work_POWER10;
> /* segment page size remain the same */
> pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->radix_page_info = &POWER10_radix_page_info;
> @@ -8796,6 +8800,12 @@ static bool ppc_cpu_has_work(CPUState *cs)
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = &cpu->env;
>
> + if (cs->halted) {
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> +
> + return pcc->has_work(cs);
> + }
> +
> return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> }
> #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-09-03 0:56 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 16:15 [PATCH v3 00/30] accel: Move has_work() from SysemuCPUOps to AccelOpsClass Philippe Mathieu-Daudé
2021-09-02 16:15 ` [PATCH v3 01/30] accel/tcg: Restrict cpu_handle_halt() to sysemu Philippe Mathieu-Daudé
2021-09-03 19:31 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 02/30] hw/core: Restrict cpu_has_work() " Philippe Mathieu-Daudé
2021-09-03 20:11 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 03/30] hw/core: Un-inline cpu_has_work() Philippe Mathieu-Daudé
2021-09-03 20:11 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 04/30] sysemu: Introduce AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-03 20:14 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 05/30] accel/kvm: Implement AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-03 20:15 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 06/30] accel/whpx: " Philippe Mathieu-Daudé
2021-09-03 20:16 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 07/30] accel/tcg: Implement AccelOpsClass::has_work() as stub Philippe Mathieu-Daudé
2021-09-03 20:17 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 08/30] target/alpha: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-03 20:18 ` Richard Henderson
2021-09-03 20:34 ` Philippe Mathieu-Daudé
2021-09-03 20:38 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 09/30] target/arm: " Philippe Mathieu-Daudé
2021-09-03 20:19 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 10/30] target/avr: " Philippe Mathieu-Daudé
2021-09-03 20:20 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 11/30] target/cris: " Philippe Mathieu-Daudé
2021-09-03 20:21 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 12/30] target/hexagon: Remove unused has_work() handler Philippe Mathieu-Daudé
2021-09-03 20:21 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 13/30] target/hppa: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-03 20:22 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 14/30] target/i386: " Philippe Mathieu-Daudé
2021-09-03 20:23 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 15/30] target/m68k: " Philippe Mathieu-Daudé
2021-09-03 20:24 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 16/30] target/microblaze: " Philippe Mathieu-Daudé
2021-09-03 20:25 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 17/30] target/mips: " Philippe Mathieu-Daudé
2021-09-03 20:26 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 18/30] target/nios2: " Philippe Mathieu-Daudé
2021-09-03 20:31 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 19/30] target/openrisc: " Philippe Mathieu-Daudé
2021-09-03 20:31 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 20/30] target/ppc: " Philippe Mathieu-Daudé
2021-09-03 0:49 ` David Gibson
2021-09-03 20:43 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 21/30] target/ppc: Introduce PowerPCCPUClass::has_work() Philippe Mathieu-Daudé
2021-09-03 0:50 ` David Gibson [this message]
2021-09-03 20:38 ` Philippe Mathieu-Daudé
2021-09-03 20:42 ` Richard Henderson
2021-09-03 21:11 ` Philippe Mathieu-Daudé
2021-09-11 22:31 ` Philippe Mathieu-Daudé
2021-09-12 12:31 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 22/30] target/ppc: Simplify has_work() handlers Philippe Mathieu-Daudé
2021-09-03 20:43 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 23/30] target/riscv: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-03 20:43 ` Richard Henderson
2021-09-02 16:15 ` [PATCH v3 24/30] target/rx: " Philippe Mathieu-Daudé
2021-09-03 20:44 ` Richard Henderson
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