Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO

Jean-Philippe Brucker
2021-10-14T09:17:07Z

On Thu, Oct 14, 2021 at 08:01:49AM +0000, Tian, Kevin wrote:
> > From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > Sent: Thursday, September 30, 2021 6:33 PM
> >
> > The PTE flags define whether the memory access is cache-coherent or not.
> > * WB is cacheable (short for write-back cacheable. Doesn't matter here
> > what OI or RWA mean.)
> > * NC is non-cacheable.
> >
> > | Normal PCI access | No_snoop PCI access
> > -------+-------------------+-------------------
> > PTE WB | Cacheable | Non-cacheable
> > PTE NC | Non-cacheable | Non-cacheable
>
> This implies that PCI no-snoop supersedes PTE flags when it's supported
> by the system?
>

Yes, no way for the SMMU to ignore no-snoop, as far as I can see

Thanks,
Jean