RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO

Tian, Kevin
2021-10-14T08:02:08Z

> From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> Sent: Thursday, September 30, 2021 6:33 PM
>
> The PTE flags define whether the memory access is cache-coherent or not.
> * WB is cacheable (short for write-back cacheable. Doesn't matter here
> what OI or RWA mean.)
> * NC is non-cacheable.
>
> | Normal PCI access | No_snoop PCI access
> -------+-------------------+-------------------
> PTE WB | Cacheable | Non-cacheable
> PTE NC | Non-cacheable | Non-cacheable

This implies that PCI no-snoop supersedes PTE flags when it's supported
by the system?