Re: [PATCH 04/11] PCI: portdrv: Suppress kernel DMA ownership auto-claiming

Jason Gunthorpe
2021-11-16T20:48:38Z

On Tue, Nov 16, 2021 at 02:22:01PM -0600, Bjorn Helgaas wrote:
> On Tue, Nov 16, 2021 at 03:24:29PM +0800, Lu Baolu wrote:
> > On 2021/11/16 4:44, Bjorn Helgaas wrote:
> > > On Mon, Nov 15, 2021 at 10:05:45AM +0800, Lu Baolu wrote:
> > > > IOMMU grouping on PCI necessitates that if we lack isolation on a bridge
> > > > then all of the downstream devices will be part of the same IOMMU group
> > > > as the bridge.
> > >
> > > I think this means something like: "If a PCIe Switch Downstream Port
> > > lacks <a specific set of ACS capabilities>, all downstream devices
> > > will be part of the same IOMMU group as the switch," right?
> >
> > For this patch, yes.
> >
> > > If so, can you fill in the details to make it specific and concrete?
> >
> > The existing vfio implementation allows a kernel driver to bind with a
> > PCI bridge while its downstream devices are assigned to the user space
> > though there lacks ACS-like isolation in bridge.
> >
> > drivers/vfio/vfio.c:
> > 540 static bool vfio_dev_driver_allowed(struct device *dev,
> > 541 struct device_driver *drv)
> > 542 {
> > 543 if (dev_is_pci(dev)) {
> > 544 struct pci_dev *pdev = to_pci_dev(dev);
> > 545
> > 546 if (pdev->hdr_type != PCI_HEADER_TYPE_NORMAL)
> > 547 return true;
> > 548 }
> >
> > We are moving the group viability check to IOMMU core, and trying to
> > make it compatible with the current vfio policy. We saw three types of
> > bridges:
> >
> > #1) PCIe/PCI-to-PCI bridges
> > These bridges are configured in the PCI framework, there's no
> > dedicated driver for such devices.
> >
> > #2) Generic PCIe switch downstream port
> > The port driver doesn't map and access any MMIO in the PCI BAR.
> > The iommu group is viable to user even this driver is bound.
> >
> > #3) Hot Plug Controller
> > The controller driver maps and access the device MMIO. The iommu
> > group is not viable to user with this driver bound to its device.
>
> I *guess* the question here is whether the bridge can or will do DMA?
> I think that's orthogonal to the question of whether it implements
> BARs, so I'm not sure why the MMIO BARs are part of this discussion.
> I assume it's theoretically possible for a driver to use registers in
> config space to program a device to do DMA, even if the device has no
> BARs.

There are two questions Lu is trying to get at:

1) Does the bridge driver use DMA? Calling pci_set_master() or
a dma_map_* API is a sure indicate the driver is doing DMA

Kernel DMA doesn't work if the PCI device is attached to
non-default iommu domain.

2) If the bridge driver uses MMIO, is it tolerant to hostile
userspace also touching the same MMIO registers via P2P DMA
attacks?

Conservatively if the driver maps a MMIO region at all
we can say it fails this test.

Unless someone want to do the audit work, identifying MMIO usage alone
is sufficient to disqualify a driver.

Jason