[PATCH v2 19/25] KVM: x86/mmu: simplify and/or inline computation of shadow MMU roles

Paolo Bonzini
2022-02-21T16:23:35Z

Shadow MMUs compute their role from cpu_mode.base, simply by adjusting
the root level. It's one line of code, so do not place it in a separate
function.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/kvm/mmu/mmu.c | 54 +++++++++++++++---------------------------
1 file changed, 19 insertions(+), 35 deletions(-)

diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index d657e2e2ceec..47288643ab70 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4768,30 +4768,6 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu,
reset_tdp_shadow_zero_bits_mask(context);
}

-static union kvm_mmu_page_role
-kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
- union kvm_mmu_paging_mode role)
-{
- if (!role.ext.efer_lma)
- role.base.level = PT32E_ROOT_LEVEL;
- else if (role.ext.cr4_la57)
- role.base.level = PT64_ROOT_5LEVEL;
- else
- role.base.level = PT64_ROOT_4LEVEL;
-
- /*
- * KVM forces EFER.NX=1 when TDP is disabled, reflect it in the MMU role.
- * KVM uses NX when TDP is disabled to handle a variety of scenarios,
- * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
- * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
- * The iTLB multi-hit workaround can be toggled at any time, so assume
- * NX can be used by any non-nested shadow MMU to avoid having to reset
- * MMU contexts.
- */
- role.base.efer_nx = true;
- return role.base;
-}
-
static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
union kvm_mmu_paging_mode cpu_mode,
union kvm_mmu_page_role root_role)
@@ -4822,18 +4798,23 @@ static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
{
struct kvm_mmu *context = &vcpu->arch.root_mmu;
union kvm_mmu_paging_mode cpu_mode = kvm_calc_cpu_mode(vcpu, regs);
- union kvm_mmu_page_role root_role =
- kvm_calc_shadow_mmu_root_page_role(vcpu, cpu_mode);
+ union kvm_mmu_page_role root_role;

- shadow_mmu_init_context(vcpu, context, cpu_mode, root_role);
-}
+ root_role = cpu_mode.base;
+ root_role.level = max_t(u32, root_role.level, PT32E_ROOT_LEVEL);

-static union kvm_mmu_page_role
-kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
- union kvm_mmu_paging_mode role)
-{
- role.base.level = kvm_mmu_get_tdp_level(vcpu);
- return role.base;
+ /*
+ * KVM forces EFER.NX=1 when TDP is disabled, reflect it in the MMU role.
+ * KVM uses NX when TDP is disabled to handle a variety of scenarios,
+ * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
+ * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
+ * The iTLB multi-hit workaround can be toggled at any time, so assume
+ * NX can be used by any non-nested shadow MMU to avoid having to reset
+ * MMU contexts.
+ */
+ root_role.efer_nx = true;
+
+ shadow_mmu_init_context(vcpu, context, cpu_mode, root_role);
}

void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
@@ -4846,7 +4827,10 @@ void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
.efer = efer,
};
union kvm_mmu_paging_mode cpu_mode = kvm_calc_cpu_mode(vcpu, &regs);
- union kvm_mmu_page_role root_role = kvm_calc_shadow_npt_root_page_role(vcpu, cpu_mode);
+ union kvm_mmu_page_role root_role;
+
+ root_role = cpu_mode.base;
+ root_role.level = kvm_mmu_get_tdp_level(vcpu);

shadow_mmu_init_context(vcpu, context, cpu_mode, root_role);
kvm_mmu_new_pgd(vcpu, nested_cr3);
--
2.31.1