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[35.230.65.123]) by smtp.gmail.com with ESMTPSA id o12-20020a170902778c00b0016d1f474653sm1495911pll.52.2022.07.21.07.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 07:11:12 -0700 (PDT) Date: Thu, 21 Jul 2022 14:11:08 +0000 From: Sean Christopherson To: Maxim Levitsky Cc: kvm@vger.kernel.org, x86@kernel.org, Kees Cook , Dave Hansen , linux-kernel@vger.kernel.org, "H. Peter Anvin" , Borislav Petkov , Joerg Roedel , Ingo Molnar , Paolo Bonzini , Thomas Gleixner , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson Subject: Re: [PATCH v2 05/11] KVM: x86: emulator: update the emulation mode after CR0 write Message-ID: References: <20220621150902.46126-1-mlevitsk@redhat.com> <20220621150902.46126-6-mlevitsk@redhat.com> <532c71cbca049004bd6860508fdc056ae118ab1f.camel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <532c71cbca049004bd6860508fdc056ae118ab1f.camel@redhat.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Jul 21, 2022, Maxim Levitsky wrote: > On Wed, 2022-07-20 at 23:50 +0000, Sean Christopherson wrote: > > On Tue, Jun 21, 2022, Maxim Levitsky wrote: > > > CR0.PE toggles real/protected mode, thus its update > > > should update the emulation mode. > > > > > > This is likely a benign bug because there is no writeback > > > of state, other than the RIP increment, and when toggling > > > CR0.PE, the CPU has to execute code from a very low memory address. > > > > > > Signed-off-by: Maxim Levitsky > > > --- > > > arch/x86/kvm/emulate.c | 13 ++++++++++++- > > > 1 file changed, 12 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c > > > index 6f4632babc4cd8..002687d17f9364 100644 > > > --- a/arch/x86/kvm/emulate.c > > > +++ b/arch/x86/kvm/emulate.c > > > @@ -3659,11 +3659,22 @@ static int em_movbe(struct x86_emulate_ctxt *ctxt) > > > > > > static int em_cr_write(struct x86_emulate_ctxt *ctxt) > > > { > > > - if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) > > > + int cr_num = ctxt->modrm_reg; > > > + int r; > > > + > > > + if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) > > > return emulate_gp(ctxt, 0); > > > > > > /* Disable writeback. */ > > > ctxt->dst.type = OP_NONE; > > > + > > > + if (cr_num == 0) { > > > + /* CR0 write might have updated CR0.PE */ > > > > Or toggled CR0.PG. > > I thought about it but paging actually does not affect the CPU mode. Toggling CR0.PG when EFER.LME=1 (and CR4.PAE=1) switches the CPU in and out of long mode. That's why I mentioned the EFER.LMA thing below. It's also notable in that the only reason we don't have to handle CR4 here is because clearing CR4.PAE while long is active causes a #GP. > E.g if you are in protected mode, instructions execute the same regardless > if you have paging or not. > > (There are probably some exceptions but you understand what I mean). > > Best regards, > Maxim Levitsky > > > It's probably also worth noting that ->set_cr() handles side > > effects to other registers, e.g. the lack of an EFER.LMA update makes this look > > suspicious at first glance.