Re: [PATCH v2 1/7] perf/x86/core: Update x86_pmu.pebs_capable for ICELAKE_{X,D}

Like Xu
2022-08-16T12:08:11Z

On 15/8/2022 10:30 pm, Peter Zijlstra wrote:
> On Mon, Aug 15, 2022 at 09:06:01AM -0400, Liang, Kan wrote:
>
>> Goldmont Plus should be the only platform which supports extended PEBS
>> but doesn't have Baseline.
>
> Like so then...
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2db93498ff71..cb98a05ee743 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6291,10 +6291,8 @@ __init int intel_pmu_init(void)
> x86_pmu.pebs_aliases = NULL;
> x86_pmu.pebs_prec_dist = true;
> x86_pmu.pebs_block = true;
> - x86_pmu.pebs_capable = ~0ULL;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
> - x86_pmu.flags |= PMU_FL_PEBS_ALL;
> x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
> x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
>
> @@ -6337,10 +6335,8 @@ __init int intel_pmu_init(void)
> x86_pmu.pebs_aliases = NULL;
> x86_pmu.pebs_prec_dist = true;
> x86_pmu.pebs_block = true;
> - x86_pmu.pebs_capable = ~0ULL;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
> - x86_pmu.flags |= PMU_FL_PEBS_ALL;
> x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
> x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
> x86_pmu.lbr_pt_coexist = true;
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index ba60427caa6d..ac6dd4c96dbc 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2262,6 +2262,7 @@ void __init intel_ds_init(void)
> PERF_SAMPLE_BRANCH_STACK |
> PERF_SAMPLE_TIME;
> x86_pmu.flags |= PMU_FL_PEBS_ALL;
> + x86_pmu.pebs_capable = ~0ULL;
> pebs_qual = "-baseline";
> x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
> } else {

Looks good to me.

This diff touches PMU_FL_PEBS_ALL, which is less needed for guest PEBS fixes.
It has be sent out separately to the linux-perf-users group for further review.