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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id m18-20020a170902f65200b001732a019dddsm9957288plg.174.2022.08.30.10.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 10:40:36 -0700 (PDT) Date: Tue, 30 Aug 2022 17:40:32 +0000 From: Sean Christopherson To: Like Xu Cc: Paolo Bonzini , Jim Mattson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH RESEND v2 1/8] perf/x86/core: Completely disable guest PEBS via guest's global_ctrl Message-ID: References: <20220823093221.38075-1-likexu@tencent.com> <20220823093221.38075-2-likexu@tencent.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220823093221.38075-2-likexu@tencent.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, Aug 23, 2022, Like Xu wrote: > From: Like Xu > > When a guest PEBS counter is cross-mapped by a host counter, software > will remove the corresponding bit in the arr[global_ctrl].guest and > expect hardware to perform a change of state "from enable to disable" > via the msr_slot[] switch during the vmx transaction. > > The real world is that if user adjust the counter overflow value small > enough, it still opens a tiny race window for the previously PEBS-enabled > counter to write cross-mapped PEBS records into the guest's PEBS buffer, > when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff) > to switch into the enabled state, while the arr[pebs_enable].guest has not. > > Close this window by clearing invalid bits in the arr[global_ctrl].guest. > > Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") > Signed-off-by: Like Xu > --- > arch/x86/events/intel/core.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 2db93498ff71..75cdd11ab014 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -4052,8 +4052,9 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) > /* Disable guest PEBS if host PEBS is enabled. */ > arr[pebs_enable].guest = 0; > } else { > - /* Disable guest PEBS for cross-mapped PEBS counters. */ > + /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ > arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; > + arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; > /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ > arr[global_ctrl].guest |= arr[pebs_enable].guest; > } Please post this as a separate patch to the perf folks (Cc: kvm@).