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AJvYcCUX+pAx9lEI7FDzggwtehKG1TzYysq6bNREl3q+SDWNeus//u2J2H5YL9BbJ/eVA2fuhhw=@vger.kernel.org X-Gm-Message-State: AOJu0YypeedaP1fFQtmvV+1Shfx8Uvz2pc5TXw2qSAa+MnMvAc95HlNP 5HGrblfWYFIf5vLUCQeIQBUSNfa03p008NKIYl9BWM81rH3zTQ13mQl2jcoFn5TSa+m0z0PV+U1 DeQ== X-Google-Smtp-Source: AGHT+IEi6HkFlEFq3xKkt+jYe06aQPZQAI1q0x52+uNtuIUhdse4C8DHeK4AS2iUYEs4jzZhoqPFjPm9tdI= X-Received: from pfvx11.prod.google.com ([2002:a05:6a00:270b:b0:725:dec7:dd47]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:2886:b0:728:b601:86ee with SMTP id d2e1a72fcca58-730351ec0acmr5339138b3a.16.1738770662738; Wed, 05 Feb 2025 07:51:02 -0800 (PST) Date: Wed, 5 Feb 2025 07:51:01 -0800 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250201011400.669483-1-seanjc@google.com> <20250201011400.669483-2-seanjc@google.com> <43f702b383fb99d435f2cdb8ef35cc1449fe6c23.camel@infradead.org> Message-ID: Subject: Re: [PATCH 1/5] KVM: x86/xen: Restrict hypercall MSR to unofficial synthetic range From: Sean Christopherson To: David Woodhouse Cc: Paolo Bonzini , Paul Durrant , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, syzbot+cdeaeec70992eca2d920@syzkaller.appspotmail.com, Joao Martins Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, Feb 05, 2025, David Woodhouse wrote: > On Wed, 2025-02-05 at 07:06 -0800, Sean Christopherson wrote: > > On Wed, Feb 05, 2025, David Woodhouse wrote: > > > Especially as there is a corresponding requirement that they never be= set > > > from host context (which is where the potential locking issues come i= n). > > > Which train of thought leads me to ponder this as an alternative (or > > > additional) solution: > > >=20 > > > --- a/arch/x86/kvm/x86.c > > > +++ b/arch/x86/kvm/x86.c > > > @@ -3733,7 +3733,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, = struct msr_data *msr_info) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u32 msr =3D msr_info->inde= x; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u64 data =3D msr_info->dat= a; > > > =C2=A0 > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (msr && msr =3D=3D vcpu->kvm= ->arch.xen_hvm_config.msr) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Do not allow host-initi= ated writes to trigger the Xen hypercall > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * page setup; it could in= cur locking paths which are not expected > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * if userspace sets the M= SR in an unusual location. > >=20 > > That's just as likely to break userspace.=C2=A0 Doing a save/restore on= the MSR doesn't > > make a whole lot of sense since it's effectively a "command" MSR, but I= MO it's not > > any less likely than userspace putting the MSR index outside of the syn= thetic range. >=20 > Save/restore on the MSR makes no sense. It's a write-only MSR; writing > to it has no effect *other* than populating the target page. In KVM we > don't implement reading from it at all; I don't think Xen does either? Hah, that's another KVM bug, technically. KVM relies on the MSR not being = handled in order to generate the write-only semantics, but if the MSR index collide= s with an MSR that KVM emulates, then the MSR would be readable. KVM supports Hyp= er-V's HV_X64_MSR_TSC_INVARIANT_CONTROL (0x40000118), so just a few hundred more M= SRs until fireworks :-) If we want to close that hole, it'd be easy enough to add a check in kvm_get_msr_common(). > Those two happen in reverse chronological order, don't they? And in the > lower one the comment tells you that hyperv_enabled() doesn't work yet. > When the higher one is called later, it calls kvm_xen_init() *again* to > put the MSR in the right place. >=20 > It could be prettier, but I don't think it's broken, is it? Gah, -ENOCOFFEE. > > Userspace breakage aside, disallowng host writes would fix the immediat= e issue, > > and I think would mitigate all concerns with putting the host at risk.= =C2=A0 But it's > > not enough to actually make an overlapping MSR index work.=C2=A0 E.g. i= f the MSR is > > passed through to the guest, the write will go through to the hardware = MSR, unless > > the WRMSR happens to be emulated. > >=20 > > I really don't want to broadly support redirecting any MSR, because to = truly go > > down that path we'd need to deal with x2APIC, EFER, and other MSRs that= have > > special treatment and meaning. > >=20 > > While KVM's stance is usually that a misconfigured vCPU model is usersp= ace's > > problem, in this case I don't see any value in letting userspace be stu= pid.=C2=A0 It > > can't work generally, it creates unique ABI for KVM_SET_MSRS, and unles= s there's > > a crazy use case I'm overlooking, there's no sane reason for userspace = to put the > > index in outside of the synthetic range (whereas defining seemingly non= sensical > > CPUID feature bits is useful for testing purposes, implementing support= in > > userspace, etc). >=20 > Right, I think we should do *both*. Blocking host writes solves the > issue of locking problems with the hypercall page setup. All it would > take for that issue to recur is for us (or Microsoft) to invent a new > MSR in the synthetic range which is also written on vCPU init/reset. > And then the sanity check on where the VMM puts the Xen MSR doesn't > save us. Ugh, indeed. MSRs are quite the conundrum. Userspace MSR filters have a s= imilar problem, where it's impossible to know the semantics of future hardware MSR= s, and so it's impossible to document which MSRs userspace is allowed to intercept= :-/ Oh! It doesn't help KVM avoid breaking userspace, but a way for QEMU to av= oid a future collision would be to have QEMU start at 0x40000200 when Hyper-V is = enabled, but then use KVM_GET_MSR_INDEX_LIST to detect a collision with KVM Hyper-V,= e.g. increment the index until an available index is found (with sanity checks a= nd whatnot). > But yes, we should *also* do that sanity check. Ah, I'm a-ok with that.