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Thu, 20 Mar 2025 13:02:56 -0700 Date: Thu, 20 Mar 2025 13:02:54 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Yi Liu , , , , , , , , , Subject: Re: [PATCH v8 4/5] iommufd: Extend IOMMU_GET_HW_INFO to report PASID capability Message-ID: References: <20250313124753.185090-1-yi.l.liu@intel.com> <20250313124753.185090-5-yi.l.liu@intel.com> <444284f3-2dae-4aa9-a897-78a36e1be3ca@intel.com> <20250320185726.GF206770@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250320185726.GF206770@nvidia.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|MN0PR12MB5810:EE_ X-MS-Office365-Filtering-Correlation-Id: 71423fb2-7bd9-44f5-427f-08dd67ea39b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2025 20:03:04.3679 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71423fb2-7bd9-44f5-427f-08dd67ea39b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5810 On Thu, Mar 20, 2025 at 03:57:26PM -0300, Jason Gunthorpe wrote: > On Thu, Mar 20, 2025 at 09:47:32AM -0700, Nicolin Chen wrote: > > > In that regard, honestly, I don't quite get this out_capabilities. > > Yeah, I think it is best thought of as place to put discoverability if > people want discoverability. > > I have had a wait and see feeling in this area since I don't know what > qemu or libvirt would actually use. Both ARM and Intel have max_pasid_log2 being reported somewhere in their vendor data structures. So, unless user space really wants that info immediately without involving the vendor IOMMU, this max_pasid_log2 seems to be redundant. Also, this patch polls two IOMMU caps out of pci_pasid_status() that is a per device function. Is this okay? Can it end up with two devices (one has PASID; the other doesn't) behind the same IOMMU reporting two different sets of out_capabilities, which were supposed to be the same since it the same IOMMU HW? Thanks Nicolin