From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 498E2C7EE2E for ; Mon, 12 Jun 2023 19:36:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237520AbjFLTgy (ORCPT ); Mon, 12 Jun 2023 15:36:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229480AbjFLTgs (ORCPT ); Mon, 12 Jun 2023 15:36:48 -0400 Received: from out-32.mta0.migadu.com (out-32.mta0.migadu.com [91.218.175.32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F243F0 for ; Mon, 12 Jun 2023 12:36:43 -0700 (PDT) Date: Mon, 12 Jun 2023 21:36:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1686598600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=sHOwRria8WiDlXjDW/If+zix7QRbjzZycNIlyopWw1E=; b=Nj+wHbsVq4H20uyeoZmzpV3GNcl+aFzofDCBDUjH8vFfG4bXqmwGfba/FxsZ6f85vVQkNG auPFdIo+2EyWYeqMP52EbjfW4bPtAO7c8YmtM5iqaBcW7Dk+CKeHhnu3yvwm7DOMtzZEd2 /AFLIrJncbFjbydlQWl6+teycrVojzE= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Reiji Watanabe Cc: Marc Zyngier , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH 1/1] KVM: arm64: PMU: Avoid inappropriate use of host's PMUVer Message-ID: References: <20230610194510.4146549-1-reijiw@google.com> <20230611045430.evkcp4py4yuw5qgr@google.com> <20230611160105.orvjohigsaevkcrf@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230611160105.orvjohigsaevkcrf@google.com> X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Sun, Jun 11, 2023 at 09:01:05AM -0700, Reiji Watanabe wrote: [...] > > Suppose KVM is running on a v3p5+ implementation, but userspace has set > > ID_AA64DFR0_EL1.PMUVer to v3p0. In this case the read of PMCEID1_EL0 on > > the preceding line would advertise the STALL_SLOT event, and KVM fails > > to mask it due to the ID register value. The fact we do not support the > > event is an invariant, in the worst case we wind up clearing a bit > > that's already 0. > > As far as I checked ArmARM, the STALL_SLOT event can be supported on > any PMUv3 version (including on v3p0). Assuming that is true, I don't > see any reason to not expose the event to the guest in this particular > example. Or can the STALL_SLOT event only be implemented from certain > versions of PMUv3 ? Well, users of the event don't get the full picture w/o PMMIR_EL1.SLOTS, which is only available on v3p4+. We probably should start exposing the register + event (separate from this change). > > This is why I'd suggested just unconditionally clearing the bit. While > > When the hardware supports the STALL_SLOT event (again, I assume any > PMUv3 version hardware can support the event), and the guest's PMUVer > is older than v3p4, what is the reason why we want to clear the bit ? What's the value of the event w/o PMMIR_EL1? I agree there's no fundamental issue with letting it past, but I'd rather we start exposing the feature when we provide all the necessary detail. -- Thanks, Oliver