From: Sean Christopherson <seanjc@google.com>
To: Xiong Zhang <xiong.y.zhang@intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
pbonzini@redhat.com, peterz@infradead.org,
like.xu.linux@gmail.com, kan.liang@linux.intel.com,
zhenyuw@linux.intel.com, zhiyuan.lv@intel.com
Subject: Re: [PATCH 2/4] KVM: VMX/pmu: Save host debugctlmsr just before vm entry
Date: Fri, 23 Jun 2023 13:15:20 -0700 [thread overview]
Message-ID: <ZJX9WHFPdEVjRtC+@google.com> (raw)
In-Reply-To: <20230616113353.45202-3-xiong.y.zhang@intel.com>
On Fri, Jun 16, 2023, Xiong Zhang wrote:
> Perf defines four types of perf event: per cpu pinned event, per process
> pinned event, per cpu event, per process event, their prioirity are from
> high to low. vLBR event is per process pinned event. So durng vm exit
> handler, if vLBR event preempts perf low priority LBR event, perf will
> disable LBR and let guest control LBR, or if vLBR event is preempted by
> perf high priority LBR event, perf will enable LBR. In a word LBR status
> may be changed during vm exit handler.
>
> MSR_IA32_DEBUGCTLMSR[0] controls LBR enabling, kvm saves its value into
> vmx->host_debugctlmsr in vcpu_load(), and kvm restores its value from
> vmx->host_debugctlmsr after vm exit immediately. Since
> MSR_IA32_DEBUGCTLMSR[0] could be changed during vm exit handler, the
> saved value vmx->host_debugctlmsr could be wrong. So this commit saves
> MSR_IA32_DEBUGCTLMSR into vmx->host_debugctlmsr just before vm entry to
> reflect the real hardware value.
>
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
> ---
> arch/x86/kvm/vmx/vmx.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 44fb619803b8..5ca61a26d0d7 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1459,13 +1459,9 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
> */
> static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
> {
> - struct vcpu_vmx *vmx = to_vmx(vcpu);
> -
> vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
>
> vmx_vcpu_pi_load(vcpu, cpu);
> -
> - vmx->host_debugctlmsr = get_debugctlmsr();
> }
>
> static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
> @@ -7273,6 +7269,7 @@ static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
> atomic_switch_perf_msrs(vmx);
> if (intel_pmu_lbr_is_enabled(vcpu))
> vmx_passthrough_lbr_msrs(vcpu);
> + vmx->host_debugctlmsr = get_debugctlmsr();
Reading DEBUG_CTL on every VM-Entry is either unnecessary or insufficient. If
the DEBUG_CTL value is being changed synchronously, then just fix whatever KVM
path leads to a change in the host avlue. If DEBUG_CTL is being changed
asynchronously, then I'm guessing the change is coming from NMI context, which
means that KVM is buggy no matter how close we put this to VM-Enter.
next prev parent reply other threads:[~2023-06-23 20:15 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 11:33 [PATCH 0/4] Part of fix for host and guest LBR event coexist Xiong Zhang
2023-06-16 11:33 ` [PATCH 1/4] perf/x86/intel: Get shared reg constraints first for vLBR Xiong Zhang
2023-06-28 4:25 ` Like Xu
2023-06-29 2:11 ` Zhang, Xiong Y
2023-06-16 11:33 ` [PATCH 2/4] KVM: VMX/pmu: Save host debugctlmsr just before vm entry Xiong Zhang
2023-06-23 20:15 ` Sean Christopherson [this message]
2023-06-25 4:03 ` Zhang, Xiong Y
2023-06-28 5:37 ` Like Xu
2023-06-16 11:33 ` [PATCH 3/4] KVM: VMX/pmu: Enable inactive vLBR event in guest LBR MSR emulation Xiong Zhang
2023-06-23 20:38 ` Sean Christopherson
2023-06-25 6:54 ` Zhang, Xiong Y
2023-06-26 17:00 ` Sean Christopherson
2023-06-27 3:29 ` Zhang, Xiong Y
2023-06-27 15:07 ` Sean Christopherson
2023-06-28 6:07 ` Like Xu
2023-06-28 5:50 ` Like Xu
2023-06-16 11:33 ` [PATCH 4/4] KVM: selftests: Add test case for guest and host LBR preemption Xiong Zhang
2023-06-28 6:27 ` Like Xu
2023-06-29 2:39 ` Zhang, Xiong Y
2023-06-28 9:27 ` Yang, Weijiang
2023-06-29 2:52 ` Zhang, Xiong Y
2023-06-30 2:05 ` Yang, Weijiang
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