From: Sean Christopherson <seanjc@google.com>
To: Jinrong Liang <ljr.kernel@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Like Xu <likexu@tencent.com>,
David Matlack <dmatlack@google.com>,
Aaron Lewis <aaronlewis@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jinrong Liang <cloudliang@tencent.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 03/11] KVM: selftests: Test Intel PMU architectural events on gp counters
Date: Thu, 17 Aug 2023 15:46:31 -0700 [thread overview]
Message-ID: <ZN6jR6+jFBLLh3id@google.com> (raw)
In-Reply-To: <20230814115108.45741-4-cloudliang@tencent.com>
On Mon, Aug 14, 2023, Jinrong Liang wrote:
> +static void test_arch_events_cpuid(struct kvm_vcpu *vcpu,
> + uint8_t arch_events_bitmap_size,
> + uint8_t arch_events_unavailable_mask,
> + uint8_t idx)
> +{
> + uint64_t counter_val = 0;
> + bool is_supported;
> +
> + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH,
> + arch_events_bitmap_size);
> + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK,
> + arch_events_unavailable_mask);
> +
> + is_supported = arch_event_is_supported(vcpu, idx);
> + vcpu_args_set(vcpu, 1, intel_arch_events[idx]);
> +
> + while (run_vcpu(vcpu, &counter_val) != UCALL_DONE)
> + TEST_ASSERT_EQ(is_supported, !!counter_val);
> +}
> +
> +static void intel_check_arch_event_is_unavl(uint8_t idx)
> +{
> + uint8_t eax_evt_vec, ebx_unavl_mask, i, j;
> + struct kvm_vcpu *vcpu;
> + struct kvm_vm *vm;
> +
> + /*
> + * A brute force iteration of all combinations of values is likely to
> + * exhaust the limit of the single-threaded thread fd nums, so it's
> + * tested here by iterating through all valid values on a single bit.
> + */
> + for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++) {
> + eax_evt_vec = BIT_ULL(i);
> + for (j = 0; j < ARRAY_SIZE(intel_arch_events); j++) {
> + ebx_unavl_mask = BIT_ULL(j);
> + vm = pmu_vm_create_with_one_vcpu(&vcpu,
> + guest_measure_loop);
> + test_arch_events_cpuid(vcpu, eax_evt_vec,
> + ebx_unavl_mask, idx);
> +
> + kvm_vm_free(vm);
This is messy. If you're going to use a helper, then use the helper. If not,
then open code everything. Half and half just makes everything unnecessarily
hard to follow. E.g. if you reorganize things, and move even more checks into
the guest, I think you can end up with:
static void test_arch_events_cpuid(uint8_t i, uint8_t j, uint8_t idx)
{
uint8_t eax_evt_vec = BIT_ULL(i);
uint8_t ebx_unavl_mask = BIT_ULL(j);
struct kvm_vcpu *vcpu;
struct kvm_vm *vm;
vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_measure_loop);
vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH,
arch_events_bitmap_size);
vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK,
arch_events_unavailable_mask);
vcpu_args_set(vcpu, 1, idx);
run_vcpu(vcpu, &counter_val)
kvm_vm_free(vm);
}
static void intel_check_arch_event_is_unavl(uint8_t idx)
{
/*
* A brute force iteration of all combinations of values is likely to
* exhaust the limit of the single-threaded thread fd nums, so it's
* tested here by iterating through all valid values on a single bit.
*/
for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++) {
eax_evt_vec = BIT_ULL(i);
for (j = 0; j < ARRAY_SIZE(intel_arch_events); j++)
test_arch_events_cpuid(i, j, idx);
}
}
next prev parent reply other threads:[~2023-08-17 22:47 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-14 11:50 [PATCH v3 00/11] KVM: selftests: Test the consistency of the PMU's CPUID and its features Jinrong Liang
2023-08-14 11:50 ` [PATCH v3 01/11] KVM: selftests: Add vcpu_set_cpuid_property() to set properties Jinrong Liang
2023-08-14 11:50 ` [PATCH v3 02/11] KVM: selftests: Add pmu.h for PMU events and common masks Jinrong Liang
2023-08-17 22:32 ` Sean Christopherson
2023-08-21 8:56 ` Like Xu
2023-08-21 9:07 ` Jinrong Liang
2023-08-14 11:51 ` [PATCH v3 03/11] KVM: selftests: Test Intel PMU architectural events on gp counters Jinrong Liang
2023-08-17 22:46 ` Sean Christopherson [this message]
2023-08-17 22:54 ` Sean Christopherson
2023-08-21 11:45 ` Jinrong Liang
2023-08-14 11:51 ` [PATCH v3 04/11] KVM: selftests: Test Intel PMU architectural events on fixed counters Jinrong Liang
2023-08-17 22:56 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 05/11] KVM: selftests: Test consistency of CPUID with num of gp counters Jinrong Liang
2023-08-17 23:00 ` Sean Christopherson
2023-08-17 23:18 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 06/11] KVM: selftests: Test consistency of CPUID with num of fixed counters Jinrong Liang
2023-08-17 23:04 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 07/11] KVM: selftests: Test Intel supported fixed counters bit mask Jinrong Liang
2023-08-17 23:19 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 08/11] KVM: selftests: Test consistency of PMU MSRs with Intel PMU version Jinrong Liang
2023-08-17 23:21 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 09/11] KVM: selftests: Add x86 feature and properties for AMD PMU in processor.h Jinrong Liang
2023-08-17 23:26 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 10/11] KVM: selftests: Test AMD PMU events on legacy four performance counters Jinrong Liang
2023-08-14 11:51 ` [PATCH v3 11/11] KVM: selftests: Test AMD Guest PerfMonV2 Jinrong Liang
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