Re: KVM: X86: Make bus clock frequency for vapic timer (bus lock -> bus clock) (was Re: [PATCH 0/2] KVM: X86: Make bus lock frequency for vapic timer) configurable

[Sean Christopherson <seanjc@google.com>]

On Wed, Nov 08, 2023, Isaku Yamahata wrote:
> On Tue, Nov 07, 2023 at 12:03:35PM -0800, Jim Mattson <jmattson@google.com> wrote:
> > I think I know the answer, but do you have any tests for this new feature?
> 
> If you mean kvm kselftest, no.
> I have
> - TDX patched qemu
> - kvm-unit-tests: test_apic_timer_one_shot() @ kvm-unit-tests/x86/apic.c
>   TDX version is found at https://github.com/intel/kvm-unit-tests-tdx
>   We're planning to upstream the changes for TDX
> 
> How far do we want to go?
> - Run kvm-unit-tests with TDX. What I have right now.
> - kvm-unit-tests: extend qemu for default VM case and update
>   test_apic_timer_one_host()

Hrm, I'm not sure that we can do a whole lot for test_apic_timer_one_shot().  Or
rather, I'm not sure it's worth the effort to try and add coverage beyond what's
already there.

As for TDX, *if* we extend KUT, please don't make it depend on TDX.  Very few people
have access to TDX platforms and anything CoCo is pretty much guaranteed to be harder
to debug.

> - kselftest
>   Right now kvm kselftest doesn't have test cases even for in-kernel IRQCHIP
>   creation.

Selftests always create an in-kernel APIC.  And I think selftests are perfectly
suited to complement the coverage provided by KUT.  Specifically, the failure
scenario for this is that KVM emulates at 1Ghz whereas TDX advertises 25Mhz, i.e.
the test case we want is to verify that the APIC timer doesn't expire early.

There's no need for any APIC infrastructure, e.g. a selftest doesn't even need to
handle an interrupt.  Get the TSC frequency from KVM, program up an arbitrary APIC
bus clock frequency, set TMICT such that it expires waaaay in the future, and then
verify that the APIC timer counts reasonably close to the programmed frequency.
E.g. if the test sets the bus clock to 25Mhz, the "drift" due to KVM counting at
1Ghz should be super obvious.

LOL, side topic, KUT has this:

	/*
	 * For LVT Timer clock, SDM vol 3 10.5.4 says it should be
	 * derived from processor's bus clock (IIUC which is the same  <======
	 * as TSC), however QEMU seems to be using nanosecond. In all
	 * cases, the following should satisfy on all modern
	 * processors.
	 */
	report((lvtt_counter == 1) && (tsc2 - tsc1 >= interval),
	       "APIC LVT timer one shot");