Re: [PATCH v15 17/23] x86/kexec: Flush cache of TDX private memory

Huang, Kai
2023-11-27T22:09:49Z

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On Mon, 2023-11-27 at 13:06 -0800, Hansen, Dave wrote:
> On 11/27/23 12:52, Huang, Kai wrote:
> > --- a/arch/x86/kernel/machine_kexec_64.c
> > +++ b/arch/x86/kernel/machine_kexec_64.c
> > @@ -377,7 +377,8 @@ void machine_kexec(struct kimage *image)
> > (unsigned long)page_list,
> > image->start,
> > image->preserve_context,
> > -
> > cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT));
> > + cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)
> > > >
> > + platform_tdx_enabled());
>
> Well, something more like the attached would be preferable, but you've
> got the right idea logically.

Thanks!

On top of that, I think below code (also attached the diff) should do
advertising the CC_ATTR_HOST_MEM_INCOHERENT for TDX host?

diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
index 2e2d559169a8..bec70b967504 100644
--- a/arch/x86/coco/core.c
+++ b/arch/x86/coco/core.c
@@ -12,6 +12,8 @@

#include <asm/coco.h>
#include <asm/processor.h>
+#include <asm/cpufeatures.h>
+#include <asm/tdx.h>

enum cc_vendor cc_vendor __ro_after_init = CC_VENDOR_NONE;
static u64 cc_mask __ro_after_init;
@@ -23,7 +25,9 @@ static bool noinstr intel_cc_platform_has(enum cc_attr attr)
case CC_ATTR_HOTPLUG_DISABLED:
case CC_ATTR_GUEST_MEM_ENCRYPT:
case CC_ATTR_MEM_ENCRYPT:
- return true;
+ return cpu_feature_enabled(X86_FEATURE_TDX_GUEST);
+ case CC_ATTR_HOST_MEM_INCOHERENT:
+ return platform_tdx_enabled();
default:
return false;
}
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 73cd2f7b7d87..1ae21348edc1 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -1634,6 +1634,13 @@ static int __init tdx_init(void)
tdx_guest_keyid_start = tdx_keyid_start + 1;
tdx_nr_guest_keyids = nr_tdx_keyids - 1;

+ /*
+ * TDX doesn't guarantee cache coherency among different
+ * KeyIDs. Advertise the CC_ATTR_HOST_MEM_INCOHERENT
+ * attribute for TDX host.
+ */
+ cc_vendor = CC_VENDOR_INTEL;
+
return 0;
}
early_initcall(tdx_init);

I'll do some test with your code and the above code.

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diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
index 2e2d559169a8..bec70b967504 100644
--- a/arch/x86/coco/core.c
+++ b/arch/x86/coco/core.c
@@ -12,6 +12,8 @@

#include <asm/coco.h>
#include <asm/processor.h>
+#include <asm/cpufeatures.h>
+#include <asm/tdx.h>

enum cc_vendor cc_vendor __ro_after_init = CC_VENDOR_NONE;
static u64 cc_mask __ro_after_init;
@@ -23,7 +25,9 @@ static bool noinstr intel_cc_platform_has(enum cc_attr attr)
case CC_ATTR_HOTPLUG_DISABLED:
case CC_ATTR_GUEST_MEM_ENCRYPT:
case CC_ATTR_MEM_ENCRYPT:
- return true;
+ return cpu_feature_enabled(X86_FEATURE_TDX_GUEST);
+ case CC_ATTR_HOST_MEM_INCOHERENT:
+ return platform_tdx_enabled();
default:
return false;
}
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 73cd2f7b7d87..1ae21348edc1 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -1634,6 +1634,13 @@ static int __init tdx_init(void)
tdx_guest_keyid_start = tdx_keyid_start + 1;
tdx_nr_guest_keyids = nr_tdx_keyids - 1;

+ /*
+ * TDX doesn't guarantee cache coherency among different
+ * KeyIDs. Advertise the CC_ATTR_HOST_MEM_INCOHERENT
+ * attribute for TDX host.
+ */
+ cc_vendor = CC_VENDOR_INTEL;
+
return 0;
}
early_initcall(tdx_init);