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Tue, 28 Nov 2023 16:51:24 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 28 Nov 2023 16:51:24 -0800 Received: from Asurada-Nvidia (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend Transport; Tue, 28 Nov 2023 16:51:23 -0800 Date: Tue, 28 Nov 2023 16:51:21 -0800 From: Nicolin Chen To: "Tian, Kevin" CC: "Liu, Yi L" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "cohuck@redhat.com" , "eric.auger@redhat.com" , "kvm@vger.kernel.org" , "mjrosato@linux.ibm.com" , "chao.p.peng@linux.intel.com" , "yi.y.sun@linux.intel.com" , "peterx@redhat.com" , "jasowang@redhat.com" , "shameerali.kolothum.thodi@huawei.com" , "lulu@redhat.com" , "suravee.suthikulpanit@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "Duan, Zhenzhong" , "joao.m.martins@oracle.com" , "Zeng, Xin" , "Zhao, Yan Y" Subject: Re: [PATCH v6 2/6] iommufd: Add IOMMU_HWPT_INVALIDATE Message-ID: References: <20231117130717.19875-3-yi.l.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 00:51:41.6254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b93850fb-437b-4629-f2e0-08dbf0755a2a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9169 On Tue, Nov 28, 2023 at 08:03:35AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Tuesday, November 28, 2023 3:53 AM > > > > On Fri, Nov 24, 2023 at 02:36:29AM +0000, Tian, Kevin wrote: > > > > > > > > > > >> + * @out_driver_error_code: Report a driver speicifc error code > > > > upon > > > > > > > > failure. > > > > > > > > >> + * It's optional, driver has a choice to fill it or > > > > > > > > >> + * not. > > > > > > > > > > > > > > > > > > Being optional how does the user tell whether the code is filled > > or > > > > not? > > > > > > > > > > > > Well, naming it "error_code" indicates zero means no error while > > > > > > non-zero means something? An error return from this ioctl could > > > > > > also tell the user space to look up for this driver error code, > > > > > > if it ever cares. > > > > > > > > > > probably over-thinking but I'm not sure whether zero is guaranteed to > > > > > mean no error in all implementations... > > > > > > > > Well, you are right. Usually HW conveniently raises a flag in a > > > > register to indicate something wrong, yet it is probably unsafe > > > > to say it definitely. > > > > > > > > > > this reminds me one open. What about an implementation having > > > a hierarchical error code layout e.g. one main error register with > > > each bit representing an error category then multiple error code > > > registers each for one error category? In this case probably > > > a single out_driver_error_code cannot carry that raw information. > > > > Hmm, good point. > > > > > Instead the iommu driver may need to define a customized error > > > code convention in uapi header which is converted from the > > > raw error information. > > > > > > From this angle should we simply say that the error code definition > > > must be included in the uapi header? If raw error information can > > > be carried by this field then this hw can simply say that the error > > > code format is same as the hw spec defines. > > > > > > With that explicit information then the viommu can easily tell > > > whether error code is filled or not based on its own convention. > > > > That'd be to put this error_code field into the driver uAPI > > structure right? > > > > I also thought about making this out_driver_error_code per HW. > > Yet, an error can be either per array or per entry/quest. The > > array-related error should be reported in the array structure > > that is a core uAPI, v.s. the per-HW entry structure. Though > > we could still report an array error in the entry structure > > at the first entry (or indexed by "array->entry_num")? > > > > why would there be an array error? array is just a software > entity containing actual HW invalidation cmds. If there is > any error with the array itself it should be reported via > ioctl errno. User array reading is a software operation, but kernel array reading is a hardware operation that can raise an error when the memory location to the array is incorrect or so. With that being said, I think errno (-EIO) could do the job, as you suggested too. Thanks Nic > Jason, how about your opinion? I didn't spot big issues > except this one. Hope it can make into 6.8.