From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CDEE1842 for ; Mon, 15 Jan 2024 03:36:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cyU+ziYa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705289762; x=1736825762; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=TaFI8xu9ha7Qu9WsffH9ZV0yEhE8bI5Htv2gCGJD1D8=; b=cyU+ziYavh8jpi79Cn3Zrb77Z8A23c09yj88/YkplTH2/uJlr2f7O8Zj zu0wIrbhY1TmFZHWeAYPmXUUaDm1sgFXJIn6En2dxmRbmuExDChH+z0iF g0HPobCBwP9yZGillwJRjsI+Nx4ZWd+7Y9PztwWPU48yYL+LBHIu94PUF YxXqntaVTiF0CZUGsGzkf/L2WNyi+SjjKslimlkj4Kuns69TFOR6SKtJp +u4u8zRrnf/4P81kloXYDVEamXXJK9H3hHZhDkC7mtd37QlXaR9FfMXaK Rv5Qm/+pU7QawsqACQekiAXtxybju16SYnkqsYiwyUarCnUoMXNYLabEE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="6247489" X-IronPort-AV: E=Sophos;i="6.04,195,1695711600"; d="scan'208";a="6247489" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2024 19:36:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="1114810777" X-IronPort-AV: E=Sophos;i="6.04,195,1695711600"; d="scan'208";a="1114810777" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.36]) by fmsmga005.fm.intel.com with ESMTP; 14 Jan 2024 19:35:58 -0800 Date: Mon, 15 Jan 2024 11:48:56 +0800 From: Zhao Liu To: Xiaoyao Li Cc: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Zhao Liu , Babu Moger , Yongwei Ma Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Message-ID: References: <20240108082727.420817-1-zhao1.liu@linux.intel.com> <20240108082727.420817-16-zhao1.liu@linux.intel.com> <599ddf2d-dc2e-4684-b2c2-ba6dfd886f32@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <599ddf2d-dc2e-4684-b2c2-ba6dfd886f32@intel.com> Hi Xiaoyao, On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote: > Date: Sun, 14 Jan 2024 22:42:41 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for > CPUID[0x8000001D].EAX[bits 25:14] > > On 1/8/2024 4:27 PM, Zhao Liu wrote: > > From: Zhao Liu > > > > The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information > > for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding > > the number of sharing threads directly. > > > > From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) > > means [1]: > > > > The number of logical processors sharing this cache is the value of > > this field incremented by 1. To determine which logical processors are > > sharing a cache, determine a Share Id for each processor as follows: > > > > ShareId = LocalApicId >> log2(NumSharingCache+1) > > > > Logical processors with the same ShareId then share a cache. If > > NumSharingCache+1 is not a power of two, round it up to the next power > > of two. > > > > From the description above, the calculation of this field should be same > > as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of > > APIC ID to calculate this field. > > > > [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology > > Information > > this patch can be dropped because we have next patch. This patch is mainly used to explicitly emphasize the change in encoding way and compliance with AMD spec... I didn't tested on AMD machine, so the more granular patch would make it easier for the community to review and test. Thanks, Zhao > > > Signed-off-by: Zhao Liu > > Reviewed-by: Babu Moger > > Tested-by: Babu Moger > > Tested-by: Yongwei Ma > > Acked-by: Michael S. Tsirkin > > --- > > Changes since v3: > > * Rewrite the subject. (Babu) > > * Delete the original "comment/help" expression, as this behavior is > > confirmed for AMD CPUs. (Babu) > > * Rename "num_apic_ids" (v3) to "num_sharing_cache" to match spec > > definition. (Babu) > > > > Changes since v1: > > * Rename "l3_threads" to "num_apic_ids" in > > encode_cache_cpuid8000001d(). (Yanan) > > * Add the description of the original commit and add Cc. > > --- > > target/i386/cpu.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index b23e8190dc68..8a4d72f6f760 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -483,7 +483,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > uint32_t *eax, uint32_t *ebx, > > uint32_t *ecx, uint32_t *edx) > > { > > - uint32_t l3_threads; > > + uint32_t num_sharing_cache; > > assert(cache->size == cache->line_size * cache->associativity * > > cache->partitions * cache->sets); > > @@ -492,13 +492,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > /* L3 is shared among multiple cores */ > > if (cache->level == 3) { > > - l3_threads = topo_info->modules_per_die * > > - topo_info->cores_per_module * > > - topo_info->threads_per_core; > > - *eax |= (l3_threads - 1) << 14; > > + num_sharing_cache = 1 << apicid_die_offset(topo_info); > > } else { > > - *eax |= ((topo_info->threads_per_core - 1) << 14); > > + num_sharing_cache = 1 << apicid_core_offset(topo_info); > > } > > + *eax |= (num_sharing_cache - 1) << 14; > > assert(cache->line_size > 0); > > assert(cache->partitions > 0); >