From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A4A12566 for ; Mon, 15 Jan 2024 06:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Yk5LFxFZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705299130; x=1736835130; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Icxs9cOG0QTkV29eLd1mD8xTYSicMFjqmusnrrSXIxY=; b=Yk5LFxFZjbS4CDNuoZpyUfVU4Zp1DmztYIttPpWzpaR3/kgv6ouRcU7t M9Ds80O/DJ4AVMMjEqvlAezGuo9qGWoMgGpZLUThWLKGhLWPM6zumjodS 7ipl8AiIHSLu+sHYmkELMqENKyo+lruv8KdzeKCAyCeLQjTb10ULzJ4Ls IhXr10x5WCpPK9sCO0guviGJda/2ftqEQ+N9ylQ4VOljhZABDn34MHTr6 skaiz+FP9Bro/K7Nf2mwIwKRJen3oXrkiFIYcts7n5CR1mVscowxh+KU0 iwIjDbcrqpnxPgsY5UUFC4W96ZPvj1ujwSmoNPHnnNZ+H1bgsvB78QK+y g==; X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="6636320" X-IronPort-AV: E=Sophos;i="6.04,195,1695711600"; d="scan'208";a="6636320" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2024 22:12:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="906963749" X-IronPort-AV: E=Sophos;i="6.04,195,1695711600"; d="scan'208";a="906963749" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.36]) by orsmga004.jf.intel.com with ESMTP; 14 Jan 2024 22:12:05 -0800 Date: Mon, 15 Jan 2024 14:25:02 +0800 From: Zhao Liu To: Xiaoyao Li Cc: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Zhao Liu , Babu Moger , Yongwei Ma Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Message-ID: References: <20240108082727.420817-1-zhao1.liu@linux.intel.com> <20240108082727.420817-15-zhao1.liu@linux.intel.com> <5a004819-b9bf-4a2e-b8b3-ed238a66245a@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5a004819-b9bf-4a2e-b8b3-ed238a66245a@intel.com> Hi Xiaoyao, On Mon, Jan 15, 2024 at 12:25:19PM +0800, Xiaoyao Li wrote: > Date: Mon, 15 Jan 2024 12:25:19 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode > CPUID[4] > > On 1/15/2024 11:40 AM, Zhao Liu wrote: > > > > +{ > > > > + uint32_t num_ids = 0; > > > > + > > > > + switch (share_level) { > > > > + case CPU_TOPO_LEVEL_CORE: > > > > + num_ids = 1 << apicid_core_offset(topo_info); > > > > + break; > > > > + case CPU_TOPO_LEVEL_DIE: > > > > + num_ids = 1 << apicid_die_offset(topo_info); > > > > + break; > > > > + case CPU_TOPO_LEVEL_PACKAGE: > > > > + num_ids = 1 << apicid_pkg_offset(topo_info); > > > > + break; > > > > + default: > > > > + /* > > > > + * Currently there is no use case for SMT and MODULE, so use > > > > + * assert directly to facilitate debugging. > > > > + */ > > > > + g_assert_not_reached(); > > > > + } > > > > + > > > > + return num_ids - 1; > > > suggest to just return num_ids, and let the caller to do the -1 work. > > Emm, SDM calls the whole "num_ids - 1" (CPUID.0x4.EAX[bits 14-25]) as > > "maximum number of addressable IDs for logical processors sharing this > > cache"... > > > > So if this helper just names "num_ids" as max_lp_ids_share_the_cache, > > I'm not sure there would be ambiguity here? > > I don't think it will. > > if this function is going to used anywhere else, people will need to keep in > mind to do +1 stuff to get the actual number. > > leaving the -1 trick to where CPUID value gets encoded. let's make this > function generic. This helper is the complete pattern to get addressable IDs, this is to say, the "- 1" is also the part of this calculation. Its own meaning is self-consistent and generic enough to meet the common definitions of AMD and Intel. Thanks, Zhao