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AJvYcCVIy/1wPIew36AULWw/GRGMsDWtd+cAv7ZxKy2HCpO4WYMX3DJWBxRg32zuZooIHHfIQzrbZqTq4p/xNsl0gyun32kS X-Gm-Message-State: AOJu0YzqYEBCKyhoOBCR6VnHsdOtTr27MTgXlu0e/HvF0RzurqR3ZoLS a531kEthGz3zc77mjHsxOd+nW2ysSrAHOzAVsRt/bTdjWPgHWZVpqY5aY0HU6juwY99wFae0raa 15A== X-Google-Smtp-Source: AGHT+IHFbTJwSAhSpC3uUF8JQz3n16YUo7A4H885wDOtHYFEEJx/XZrsVfm5grmswMD0hb70zzrUqYxuU98= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1896:b0:dcc:6065:2b3d with SMTP id cj22-20020a056902189600b00dcc60652b3dmr813062ybb.8.1709136984844; Wed, 28 Feb 2024 08:16:24 -0800 (PST) Date: Wed, 28 Feb 2024 08:16:23 -0800 In-Reply-To: <12f0b643-e2e8-8a9a-b264-5c7c460f1a24@oracle.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240228024147.41573-1-seanjc@google.com> <20240228024147.41573-4-seanjc@google.com> <12f0b643-e2e8-8a9a-b264-5c7c460f1a24@oracle.com> Message-ID: Subject: Re: [PATCH 03/16] KVM: x86: Define more SEV+ page fault error bits/flags for #NPF From: Sean Christopherson To: Dongli Zhang Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Yan Zhao , Isaku Yamahata , Michael Roth , Yu Zhang , Chao Peng , Fuad Tabba , David Matlack Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 27, 2024, Dongli Zhang wrote: >=20 >=20 > On 2/27/24 18:41, Sean Christopherson wrote: > > Define more #NPF error code flags that are relevant to SEV+ (mostly SNP= ) > > guests, as specified by the APM: > >=20 > > * Bit 34 (ENC): Set to 1 if the guest=E2=80=99s effective C-bit was = 1, 0 otherwise. > > * Bit 35 (SIZEM): Set to 1 if the fault was caused by a size mismatch = between > > PVALIDATE or RMPADJUST and the RMP, 0 otherwise. > > * Bit 36 (VMPL): Set to 1 if the fault was caused by a VMPL permissio= n > > check failure, 0 otherwise. > > * Bit 37 (SSS): Set to VMPL permission mask SSS (bit 4) value if Vmp= lSSS is > > enabled. >=20 > The above bits 34-37 do not match with the bits 31,34-36 in the patch. Doh, good catch. I copy+pasted this from the APM, but the RMP bit is defin= ed slightly earlier in the APM, and I missed SSS. I'll fixup the changelog to= talk about RMO, and I think I'll add SSS in v2; at the very least, having the #d= efine will make it clear which bits are used. Thanks!