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AJvYcCVDbhJYgo+/3vAYH5iWAITLl0CfYvYc3yQZ9DDol5HVc9Hj4BcgKyWZ0m8lYMdv/xW89LGLsl1QH9qK1YoGypcyORrO X-Gm-Message-State: AOJu0YzDGMkkFVBc+WSAaqmrXhk91DEFvf8GBzFiwMzq246n0AVgyP48 cOEiQiUxDcd1Ir2SeFSAc/weUQn3SQV0jHG6JSZWJEVOLsyVvjNQ5h4e+GMyoKrFUKssC/Fs226 wuQ== X-Google-Smtp-Source: AGHT+IHUMg7l8Ba/eQMW6xc0LCY8Jqv8pilOK03SFH3Rgyd1QKq6aljjldttrmb86ym4lPSeUmJKzCzcmAs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1006:b0:dcc:94b7:a7a3 with SMTP id w6-20020a056902100600b00dcc94b7a7a3mr1065852ybt.12.1712156845316; Wed, 03 Apr 2024 08:07:25 -0700 (PDT) Date: Wed, 3 Apr 2024 08:07:23 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <62f8890cb90e49a3e0b0d5946318c0267b80c540.1708933498.git.isaku.yamahata@intel.com> Message-ID: Subject: Re: [PATCH v19 111/130] KVM: TDX: Implement callbacks for MSR operations for TDX From: Sean Christopherson To: Chao Gao Cc: isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Content-Type: text/plain; charset="us-ascii" On Wed, Apr 03, 2024, Chao Gao wrote: > On Mon, Feb 26, 2024 at 12:26:53AM -0800, isaku.yamahata@intel.com wrote: > >+bool tdx_has_emulated_msr(u32 index, bool write) > >+{ > >+ switch (index) { > >+ case MSR_IA32_UCODE_REV: > >+ case MSR_IA32_ARCH_CAPABILITIES: > >+ case MSR_IA32_POWER_CTL: > >+ case MSR_IA32_CR_PAT: > >+ case MSR_IA32_TSC_DEADLINE: > >+ case MSR_IA32_MISC_ENABLE: > >+ case MSR_PLATFORM_INFO: > >+ case MSR_MISC_FEATURES_ENABLES: > >+ case MSR_IA32_MCG_CAP: > >+ case MSR_IA32_MCG_STATUS: > >+ case MSR_IA32_MCG_CTL: > >+ case MSR_IA32_MCG_EXT_CTL: > >+ case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: > >+ case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: > >+ /* MSR_IA32_MCx_{CTL, STATUS, ADDR, MISC, CTL2} */ > >+ return true; > >+ case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: > >+ /* > >+ * x2APIC registers that are virtualized by the CPU can't be > >+ * emulated, KVM doesn't have access to the virtual APIC page. > >+ */ > >+ switch (index) { > >+ case X2APIC_MSR(APIC_TASKPRI): > >+ case X2APIC_MSR(APIC_PROCPRI): > >+ case X2APIC_MSR(APIC_EOI): > >+ case X2APIC_MSR(APIC_ISR) ... X2APIC_MSR(APIC_ISR + APIC_ISR_NR): > >+ case X2APIC_MSR(APIC_TMR) ... X2APIC_MSR(APIC_TMR + APIC_ISR_NR): > >+ case X2APIC_MSR(APIC_IRR) ... X2APIC_MSR(APIC_IRR + APIC_ISR_NR): > >+ return false; > >+ default: > >+ return true; > >+ } > >+ case MSR_IA32_APICBASE: > >+ case MSR_EFER: > >+ return !write; > >+ case 0x4b564d00 ... 0x4b564dff: > >+ /* KVM custom MSRs */ > >+ return tdx_is_emulated_kvm_msr(index, write); > >+ default: > >+ return false; > >+ } > > The only call site with a non-Null KVM parameter is: > > r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); > > Only MSR_IA32_SMBASE needs to be handled. So, this function is much more > complicated than it should be. No, because it's also used by tdx_{g,s}et_msr().