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AJvYcCWxJ90ZSfnmnTArBJ6AD0X46aJxCcKh7ji2tsktT9yA50qa+iD9MRL6euHF+LepfzzNmi2IDVNHhCItDA4WLkvUesVr X-Gm-Message-State: AOJu0YxQzdQouKPLO5D0DEzUKk/+yEhESMeqs9qb6aTYgRxLHoG7DccY 7hxI+e56RiJiaQMox2BWO4tgHQOntyWer5bxZFxEqmB+SlbWw6UDr3LesveOBLw= X-Google-Smtp-Source: AGHT+IFZBbWkrMsFlNLP4i0ZlHtJh5hiqPGMGHChZ4tL7JbCR2OzFzA8h4o1YnA4MyIHgbnWJTDA5A== X-Received: by 2002:a05:6a00:2355:b0:6e7:8322:ff8e with SMTP id j21-20020a056a00235500b006e78322ff8emr4200583pfj.30.1712784763268; Wed, 10 Apr 2024 14:32:43 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id gx21-20020a056a001e1500b006e72c8ece23sm99920pfb.191.2024.04.10.14.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 14:32:42 -0700 (PDT) Date: Wed, 10 Apr 2024 14:32:41 -0700 From: Deepak Gupta To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 07/10] riscv: add ISA extension parsing for Zcmop Message-ID: References: <20240410091106.749233-1-cleger@rivosinc.com> <20240410091106.749233-8-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240410091106.749233-8-cleger@rivosinc.com> On Wed, Apr 10, 2024 at 11:11:00AM +0200, Clément Léger wrote: >Add parsing for Zcmop ISA extension which was ratified in commit >b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual. > >Signed-off-by: Clément Léger >--- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index b7551bad341b..cff7660de268 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -86,6 +86,7 @@ > #define RISCV_ISA_EXT_ZCB 77 > #define RISCV_ISA_EXT_ZCD 78 > #define RISCV_ISA_EXT_ZCF 79 >+#define RISCV_ISA_EXT_ZCMOP 80 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 09dee071274d..f1450cd7231e 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -265,6 +265,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), > __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), > __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), >+ __RISCV_ISA_EXT_DATA(zcmop, RISCV_ISA_EXT_ZCMOP), As per spec zcmop is dependent on zca. So perhaps below ? __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZCMOP, RISCV_ISA_EXT_ZCA) > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), >-- >2.43.0 > >