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AJvYcCXY9L1p7imKeWb4hLEuQba5WROQEyCCpK2s9mBuLkozJCzyyjoLqqCsaYxZrgzx/3XSzhK/vhfYwluvpCd04ziOq+sO X-Gm-Message-State: AOJu0YwBMGRjTrjuidvw1turx6gF4vBCMzxdmQ8dis/sCfUVz3WXHXQd 0c7YBcJxInLLB6A7VqrcbU20eh0MkJhmBeQyNnX9Zl9bz6Q1RvMqtp8WHt2arQae/zCj1iYDmw/ 8WQ== X-Google-Smtp-Source: AGHT+IEoso9E1EzUZlOXERGVZBES24HUmNdhkCjXroYBDlZzz/sTnYht/qkC0ZK79I1dSTlWsUaLZS+I51w= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:e212:0:b0:61b:e2eb:f05 with SMTP id l18-20020a0de212000000b0061be2eb0f05mr75358ywe.2.1714604856835; Wed, 01 May 2024 16:07:36 -0700 (PDT) Date: Wed, 1 May 2024 16:07:35 -0700 In-Reply-To: <20240219074733.122080-23-weijiang.yang@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240219074733.122080-1-weijiang.yang@intel.com> <20240219074733.122080-23-weijiang.yang@intel.com> Message-ID: Subject: Re: [PATCH v10 22/27] KVM: VMX: Set up interception for CET MSRs From: Sean Christopherson To: Yang Weijiang Cc: pbonzini@redhat.com, dave.hansen@intel.com, x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, peterz@infradead.org, chao.gao@intel.com, rick.p.edgecombe@intel.com, mlevitsk@redhat.com, john.allen@amd.com Content-Type: text/plain; charset="us-ascii" On Sun, Feb 18, 2024, Yang Weijiang wrote: > @@ -7767,6 +7771,41 @@ static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) > vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); > } > > +static void vmx_update_intercept_for_cet_msr(struct kvm_vcpu *vcpu) > +{ > + bool incpt; > + > + if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { > + incpt = !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK); > + > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_INT_SSP_TAB, > + MSR_TYPE_RW, incpt); > + if (!incpt) > + return; Hmm, I find this is unnecessarily confusing and brittle. E.g. in the unlikely event more CET stuff comes along, this lurking return could cause problems. Why not handle S_CET and U_CET in a single common path? IMO, this is less error prone, and more clearly captures the relationship between S/U_CET, SHSTK, and IBT. Updating MSR intercepts is not a hot path, so the overhead of checking guest CPUID multiple times should be a non-issue. And eventually KVM should effectively cache all of those lookups, i.e. the cost will be negilible. bool incpt; if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { incpt = !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, incpt); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, incpt); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, incpt); vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, incpt); vmx_set_intercept_for_msr(vcpu, MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW, incpt); } if (kvm_cpu_cap_has(X86_FEATURE_SHSTK) || kvm_cpu_cap_has(X86_FEATURE_IBT)) { incpt = !guest_cpuid_has(vcpu, X86_FEATURE_IBT) && !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK); vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, incpt); vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, incpt); }