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AJvYcCVuyQ7Jn/zkuJ41ccyFez30qJIjxubAXNlg/oAcIyqME28F0/SjlsVeVOB0vqqlPra1pOij2KJAsPRg8Mt0Z3EZXl4y X-Gm-Message-State: AOJu0Ywov79Hq4qwsIF/feyZQW0YwazYWEMb99vwQXk30H+T3Kmit9Z/ QaarQ9UGou7Kui1SOabgkOOGcS2G0RYyzeoP9DRbrbeeQAVItjS6gWEsRWfglsHE2z8eRcky76d acA== X-Google-Smtp-Source: AGHT+IENeF3rnph7fc8JeZe16l04XQs7NClzQF5EuFP6FS2QG565s/9c2Vu2Uv2xY57ikBOmWZf7+kjvljw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:702:b0:dbe:d0a9:2be3 with SMTP id 3f1490d57ef6-debb95f21ecmr991296276.3.1715177610501; Wed, 08 May 2024 07:13:30 -0700 (PDT) Date: Wed, 8 May 2024 07:13:28 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-18-mizhang@google.com> <3eb01add-3776-46a8-87f7-54144692d7d7@linux.intel.com> Message-ID: Subject: Re: [PATCH v2 17/54] KVM: x86/pmu: Always set global enable bits in passthrough mode From: Sean Christopherson To: Dapeng Mi Cc: Mingwei Zhang , Paolo Bonzini , Xiong Zhang , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Wed, May 08, 2024, Dapeng Mi wrote: > > On 5/8/2024 12:36 PM, Mingwei Zhang wrote: > > if (pmu->passthrough && pmu->nr_arch_gp_counters) > > > > Since mediated passthrough PMU requires PerfMon v4 in Intel (PerfMon > > v2 in AMD), once it is enabled (pmu->passthrough = true), then global > > ctrl _must_ exist phyiscally. Regardless of whether we expose it to > > the guest VM, at reset time, we need to ensure enabling bits for GP > > counters are set (behind the screen). This is critical for AMD, since > > most of the guests are usually in (AMD) PerfMon v1 in which global > > ctrl MSR is inaccessible, but does exist and is operating in HW. > > > > Yes, if we eliminate that requirement (pmu->passthrough -> Perfmon v4 > > Intel / Perfmon v2 AMD), then this code will have to change. However, > Yeah, that's what I'm worrying about. We ever discussed to support mediated > vPMU on HW below perfmon v4. When someone implements this, he may not > notice this place needs to be changed as well, this introduces a potential > bug and we should avoid this. Just add a WARN on the PMU version. I haven't thought much about whether or not KVM should support mediated PMU for earlier hardware, but having a sanity check on the assumptions of this code is reasonable even if we don't _plan_ on supporting earlier hardware.