From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
kvm@vger.kernel.org
Subject: Re: [PATCH 10/11] KVM: arm64: nv: Honor guest hypervisor's FP/SVE traps in CPTR_EL2
Date: Mon, 3 Jun 2024 17:28:56 +0000 [thread overview]
Message-ID: <Zl39WCKpyaDmccgY@linux.dev> (raw)
In-Reply-To: <86le3mkxsp.wl-maz@kernel.org>
Hey,
On Mon, Jun 03, 2024 at 01:36:54PM +0100, Marc Zyngier wrote:
[...]
> > + /*
> > + * Layer the guest hypervisor's trap configuration on top of our own if
> > + * we're in a nested context.
> > + */
> > + if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
> > + goto write;
> > +
> > + if (guest_hyp_fpsimd_traps_enabled(vcpu))
> > + val &= ~CPACR_ELx_FPEN;
> > + if (guest_hyp_sve_traps_enabled(vcpu))
> > + val &= ~CPACR_ELx_ZEN;
>
> I'm afraid this isn't quite right. You are clearing both FPEN (resp
> ZEN) bits based on any of the two bits being clear, while what we want
> is to actually propagate the 0 bits (and only those).
An earlier version of the series I had was effectively doing this,
applying the L0 trap configuration on top of L1's CPTR_EL2. Unless I'm
missing something terribly obvious, I think this is still correct, as:
- If we're in a hyp context, vEL2's CPTR_EL2 is loaded into CPACR_EL1.
The independent EL0/EL1 enable bits are handled by hardware. All this
junk gets skipped and we go directly to writing CPTR_EL2.
- If we are not in a hyp context, vEL2's CPTR_EL2 gets folded into the
hardware value for CPTR_EL2. TGE must be 0 in this case, so there is
no conditional trap based on what EL the vCPU is in. There's only two
functional trap states at this point, hence the all-or-nothing
approach.
> What I have in my tree is something along the lines of:
>
> cptr = vcpu_sanitised_cptr_el2(vcpu);
> tmp = cptr & (CPACR_ELx_ZEN_MASK | CPACR_ELx_FPEN_MASK);
> val &= ~(tmp ^ (CPACR_ELx_ZEN_MASK | CPACR_ELx_FPEN_MASK));
My hesitation with this is it gives the impression that both trap bits
are significant, but in reality only the LSB is useful. Unless my
understanding is disastrously wrong, of course :)
Anyway, my _slight_ preference is towards keeping what I have if
possible, with a giant comment explaining the reasoning behind it. But I
can take your approach instead too.
--
Thanks,
Oliver
next prev parent reply other threads:[~2024-06-03 17:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 23:13 [PATCH 00/11] KVM: arm64: nv: FPSIMD/SVE support Oliver Upton
2024-05-31 23:13 ` [PATCH 01/11] KVM: arm64: nv: Forward FP/ASIMD traps to guest hypervisor Oliver Upton
2024-05-31 23:13 ` [PATCH 02/11] KVM: arm64: nv: Forward SVE " Oliver Upton
2024-05-31 23:13 ` [PATCH 03/11] KVM: arm64: nv: Load guest FP state for ZCR_EL2 trap Oliver Upton
2024-06-01 9:47 ` Marc Zyngier
2024-06-01 16:47 ` Oliver Upton
2024-05-31 23:13 ` [PATCH 04/11] KVM: arm64: nv: Load guest hyp's ZCR into EL1 state Oliver Upton
2024-05-31 23:13 ` [PATCH 05/11] KVM: arm64: nv: Handle ZCR_EL2 traps Oliver Upton
2024-05-31 23:13 ` [PATCH 06/11] KVM: arm64: nv: Save guest's ZCR_EL2 when in hyp context Oliver Upton
2024-05-31 23:13 ` [PATCH 07/11] KVM: arm64: nv: Use guest hypervisor's max VL when running nested guest Oliver Upton
2024-05-31 23:13 ` [PATCH 08/11] KVM: arm64: nv: Ensure correct VL is loaded before saving SVE state Oliver Upton
2024-05-31 23:13 ` [PATCH 09/11] KVM: arm64: Spin off helper for programming CPTR traps Oliver Upton
2024-05-31 23:13 ` [PATCH 10/11] KVM: arm64: nv: Honor guest hypervisor's FP/SVE traps in CPTR_EL2 Oliver Upton
2024-06-03 12:36 ` Marc Zyngier
2024-06-03 17:28 ` Oliver Upton [this message]
2024-06-04 11:14 ` Marc Zyngier
2024-06-04 17:44 ` Oliver Upton
2024-05-31 23:13 ` [PATCH 11/11] KVM: arm64: Allow the use of SVE+NV Oliver Upton
2024-06-01 10:24 ` [PATCH 00/11] KVM: arm64: nv: FPSIMD/SVE support Marc Zyngier
2024-06-01 16:57 ` Oliver Upton
2024-06-02 14:28 ` Marc Zyngier
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