Re: [RFC v2 3/7] hw/core: Add cache topology options in -smp

Markus Armbruster
2024-06-04T08:54:58Z

Zhao Liu <zhao1.liu@intel.com> writes:

> Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in
> -smp to define the cache topology for SMP system.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>

[...]

> diff --git a/qapi/machine.json b/qapi/machine.json
> index 7ac5a05bb9c9..8fa5af69b1bf 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -1746,6 +1746,23 @@
> #
> # @threads: number of threads per core
> #
> +# @l1d-cache: topology hierarchy of L1 data cache. It accepts the CPU
> +# topology enumeration as the parameter, i.e., CPUs in the same
> +# topology container share the same L1 data cache. (since 9.1)
> +#
> +# @l1i-cache: topology hierarchy of L1 instruction cache. It accepts
> +# the CPU topology enumeration as the parameter, i.e., CPUs in the
> +# same topology container share the same L1 instruction cache.
> +# (since 9.1)
> +#
> +# @l2-cache: topology hierarchy of L2 unified cache. It accepts the CPU
> +# topology enumeration as the parameter, i.e., CPUs in the same
> +# topology container share the same L2 unified cache. (since 9.1)
> +#
> +# @l3-cache: topology hierarchy of L3 unified cache. It accepts the CPU
> +# topology enumeration as the parameter, i.e., CPUs in the same
> +# topology container share the same L3 unified cache. (since 9.1)
> +#
> # Since: 6.1
> ##

The new members are all optional. What does "absent" mean? No such
cache? Some default topology?

Is this sufficiently general? Do all machines of interest have a split
level 1 cache, a level 2 cache, and a level 3 cache?

Is the CPU topology level the only cache property we'll want to
configure here? If the answer isn't "yes", then we should perhaps wrap
it in an object, so we can easily add more members later.

Two spaces between sentences for consistency, please.

> { 'struct': 'SMPConfiguration', 'data': {
> @@ -1758,7 +1775,11 @@
> '*modules': 'int',
> '*cores': 'int',
> '*threads': 'int',
> - '*maxcpus': 'int' } }
> + '*maxcpus': 'int',
> + '*l1d-cache': 'CPUTopoLevel',
> + '*l1i-cache': 'CPUTopoLevel',
> + '*l2-cache': 'CPUTopoLevel',
> + '*l3-cache': 'CPUTopoLevel' } }
>
> ##
> # @x-query-irq:
> diff --git a/system/vl.c b/system/vl.c …