[RFC v2 5/7] i386/cpu: Update cache topology with machine's configuration

Zhao Liu
2024-05-30T10:00:52Z

User will configure SMP cache topology via -smp.

For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3a2dadb4bce0..1bd1860ae625 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7764,6 +7764,27 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)

#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
+
+ if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) {
+ env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d;
+ env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d;
+ }
+
+ if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) {
+ env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i;
+ env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i;
+ }
+
+ if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) {
+ env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2;
+ env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2;
+ }
+
+ if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) {
+ env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3;
+ env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3;
+ }
+
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);

if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
--
2.34.1