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AJvYcCWFstD5C8IMzi5Xi+5LC7jpIR3ory8o0jVEtvoVilLewjOnvilBzjbEQO6beUAxX2I7gZY=@vger.kernel.org X-Gm-Message-State: AOJu0Ywq85OQX514q/6RCERXG3UwOr885d219wq5S8zM7oo0xlj5GAN0 qK17dw4NfYwBK1CbySd7t/K2OoSd/vUjUuWqY4PVoiA5bvzjHwCE9MgTGFaHoo6oBqoDvytR5kc rVQ== X-Google-Smtp-Source: AGHT+IHeXYJ6EuXxi7hKv7alTHkax3aUyhjr3AuIuyBJK0UiU+zN8QBcM1YXFltOHqLsEiVFRgye4A5+mXw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:523:b0:e02:f35c:d398 with SMTP id 3f1490d57ef6-e116cab25cfmr16532276.0.1723670548143; Wed, 14 Aug 2024 14:22:28 -0700 (PDT) Date: Wed, 14 Aug 2024 14:22:26 -0700 In-Reply-To: <67f05b7fee1c81ef4b4be62785cfd9a36df9e4c0.camel@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240812224820.34826-1-rick.p.edgecombe@intel.com> <20240812224820.34826-26-rick.p.edgecombe@intel.com> <67f05b7fee1c81ef4b4be62785cfd9a36df9e4c0.camel@intel.com> Message-ID: Subject: Re: [PATCH 25/25] KVM: x86: Add CPUID bits missing from KVM_GET_SUPPORTED_CPUID From: Sean Christopherson To: Rick P Edgecombe Cc: Chao Gao , Xiaoyao Li , "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "tony.lindgren@linux.intel.com" , Kai Huang , "isaku.yamahata@gmail.com" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, Aug 14, 2024, Rick P Edgecombe wrote: > On Wed, 2024-08-14 at 06:35 -0700, Sean Christopherson wrote: > > > One scenario where "fixed-1" bits can help is: we discover a security= issue > > > and > > > release a microcode update to expose a feature indicating which CPUs = are > > > vulnerable. if the TDX module allows the VMM to configure the feature= as 0 > > > (i.e., not vulnerable) on vulnerable CPUs, a TD might incorrectly ass= ume > > > it's > > > not vulnerable, creating a security issue. > > >=20 > > > I think in above case, the TDX module has to add a "fixed-1" bit. An = example > > > of > > > such a feature is RRSBA in the IA32_ARCH_CAPABILITIES MSR. > >=20 > > That would be fine, I would classify that as reasonable.=C2=A0 However,= that > > scenario > > doesn't really work in practice, at least not the way Intel probably ho= pes it > > plays out.=C2=A0 For the new fixed-1 bit to provide value, it would req= uire a guest > > reboot and likely a guets kernel upgrade. >=20 > If we allow "reasonable" fixed bits, we need to decide how to handle any = that > KVM sees but doesn't know about. Not filtering them is simpler to impleme= nt. > Filtering them seems a little more controlled to me. >=20 > It might depend on how reasonable, "reasonable" turns out. Maybe we give = not > filtering a try and see how it goes. If we run into a problem, we can fil= ter new > bits from that point, and add a quirk for whatever the issue is. I'm stil= l on > the fence. As I see it, it's ultimately unlikely to be KVM's problem. If Intel ships = a TDX-Module that does bad things, and someone's setup breaks when they upgra= de to that TDX-Module, then their gripe is with Intel. KVM can't do anything to = remedy the problem. If the upgrade breaks a setup because it confuses _KVM_, then I'll care, bu= t I suspect/hope that won't happen in practice, purely because KVM has so littl= e visiblity into the guest, i.e. doesn't care what is/isn't advertised to the= guest. FWIW, AMD has effectively gone the "fixed-1" route for a few things[*], e.g= . KVM can't intercept XCR0 or XSS writes. And while I detest the behavior, I hav= en't refused to merge support for SEV-ES+. I just grumble every time it comes u= p :-) [*] https://lore.kernel.org/all/ZUQvNIE9iU5TqJfw@google.com