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Wed, 11 Sep 2024 21:05:42 -0700 Date: Wed, 11 Sep 2024 21:05:40 -0700 From: Nicolin Chen To: Zhangfei Gao CC: Jason Gunthorpe , , "Hanjun Guo" , , Joerg Roedel , Kevin Tian , , Len Brown , , , Lorenzo Pieralisi , "Rafael J. Wysocki" , "Robert Moore" , Robin Murphy , "Sudeep Holla" , Will Deacon , Alex Williamson , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , , Shameerali Kolothum Thodi , Mostafa Saleh Subject: Re: [PATCH v2 0/8] Initial support for SMMUv3 nested translation Message-ID: References: <0-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|PH0PR12MB7814:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b4695a5-ef0b-4b04-9899-08dcd2e035b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+6eNplVX7WD+lZJLypmm7x5lw6GYFseJpFYNiAsqM6rEFJvUcjHYW9Zcn1Cy?= =?us-ascii?Q?Z8d+fqdEgH843sRH0/8rOK6LTc62yE2laGBoi3P7xZAn+R+W9kjx75uKThJK?= =?us-ascii?Q?x6gDgOn+rBApBUmimLhJTjcBrsdRej/X7IMgZ4U4K6AyFODRcobVHfDUru6V?= =?us-ascii?Q?uhTPZu2w0WtcI8SA6Bve0QB87fYetRWXDpUMFeJEpwiY7s4vdQp8iLQrcnnw?= =?us-ascii?Q?drr0lpC2OvXJ8P74RrEoIJYXtDBiHDFFJ3pCfoN8O+UbLYuJJYaP+5aHeMZk?= =?us-ascii?Q?unxDnE37X4J8GONLm+vwXCqDFj+d+0c2Mh3dYCVKpALr62vnly08cs/u3BNC?= =?us-ascii?Q?CQVWGEZ1Xi9IrhR72zNR7FlEPiBAHqmprpfSYwbAOvYwlgCglmrDehuc0c+O?= =?us-ascii?Q?fEeSNlfsb1ow++ZLJtR7JEqD0O8RlGxDJd6i5BJmrFRC+N//eIcMjwUz4mCb?= =?us-ascii?Q?Y9xG2WpuKNndGKUBv8s8gwT/Gr78HVT/ga/NFLGkC/0gIEwi3QOmgKdT10gB?= =?us-ascii?Q?5f5B4pylVSPQbRpxpFAa3nRptweBqUgHRWPBaRga34rfqGHMzeAsxevEV44o?= =?us-ascii?Q?wYMOMERCPHvEQK1v8o+rFIlEDuAnwCxy3qRRE7JGfcBC8GkDxyta0rU2pEvw?= =?us-ascii?Q?YlKBKnECEYoVPJ821APVRVmixtIsuxuofeqU9Rre9ScqX4LyawYj7SLf6z3q?= =?us-ascii?Q?mw49v0kufbDwSPxCYoCx1tByLhQEJuxbrPxcaZS4OKaSpwyq+NvWqLImVsD+?= =?us-ascii?Q?VA3TqT6btG8AVYBqip3KC812gYm64kmTlAA8Baflk9bgBcxpSDWtBo6gZdes?= =?us-ascii?Q?KTJiOW+VcIBeKMTHq0n+BzhQC9fSemM0a3cTQgCvwX+/wMfNSB04xYCV+JPu?= =?us-ascii?Q?rjenB6KUkvxdmUY1WwJ16Oo4SMzZ2cFGokTXVUApLSuYWiFgKHRlmN6hBdW8?= =?us-ascii?Q?H3dJRd9QScoXHou/XBLJjpQHuQbHy1wpWBAUFjMk56P10ObbcruSIXk2UtJd?= =?us-ascii?Q?CekWh1MPfAEfVzRurT3BLSqMg1ltshQvwHisjiMWQI26DE+RcICOZZhAEK/L?= =?us-ascii?Q?iJLjUddalJcjbufqgtJLAEo+UQqe3Ja5O602+qFAquebCWxGODJ/WM907nOu?= =?us-ascii?Q?XD+muuz0DvRPeFHT61nETxAyui62eL2fRNlDLhMHjHDZs3JlO3zWfWqZT4QO?= =?us-ascii?Q?hfJN9otQFW78GsQeAlgL04DVAU4boGFj0FBoaw98dWYzw+NzR5rNNGM7YUNs?= =?us-ascii?Q?FsLtBn0nK6XDDUMaVBtb+aABB7HCzK1uoL9RK+0Z7HmcBghw/OcHOvEmIzcl?= =?us-ascii?Q?sR2io6iQYp6bQEmD4yZ3IN/gL0qJOAsu5yBKO3RvNF2htymROD0uRvebO4i5?= =?us-ascii?Q?d90nX/j0nhyLRoqhMYQh/hlvObExzKoH+Pmi523S5HXhTk0iaSaDDv4oYsf5?= =?us-ascii?Q?MnXyDfVmkGNiRotMRg8bnJ5zh+k3Tomy?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 04:05:59.3765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b4695a5-ef0b-4b04-9899-08dcd2e035b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7814 On Thu, Sep 12, 2024 at 11:42:43AM +0800, Zhangfei Gao wrote: > > > The VIOMMU series is essential to allow the invalidations to be processed > > > for the CD as well. > > > > > > It is enough to allow qemu work to progress. > > > > > > This is on github: https://github.com/jgunthorpe/linux/commits/smmuv3_nesting > > > > > > v2: > > > > As mentioned above, the VIOMMU series would be required to test > > the entire nesting feature, which now has a v2 rebasing on this > > series. I tested it with a paring QEMU branch. Please refer to: > > https://lore.kernel.org/linux-iommu/cover.1724776335.git.nicolinc@nvidia.com/ > > Also, there is another new VIRQ series on top of the VIOMMU one > > and this nesting series. And I tested it too. Please refer to: > > https://lore.kernel.org/linux-iommu/cover.1724777091.git.nicolinc@nvidia.com/ > > > > With that, > > > > Tested-by: Nicolin Chen > > > Have you tested the user page fault? No, I don't have a HW to test PRI. So, I've little experience with the IOPF and its counter part in QEMU. I recall that Shameer has a series of changes in QEMU. > I got an issue, when a user page fault happens, > group->attach_handle = iommu_attach_handle_get(pasid) > return NULL. > > A bit confused here, only find IOMMU_NO_PASID is used when attaching > > __fault_domain_replace_dev > ret = iommu_replace_group_handle(idev->igroup->group, hwpt->domain, > &handle->handle); > curr = xa_store(&group->pasid_array, IOMMU_NO_PASID, handle, GFP_KERNEL); > > not find where the code attach user pasid with the attach_handle. In SMMUv3 case (the latest design), a DOMAIN_NESTED is a CD/PASID table. So one single attach_handle (domain/idev) should be enough to cover the entire thing. Please refer to: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/io-pgfault.c?h=v6.11-rc7#n127 Thanks Nicolin