[PATCH v4 6/9] i386/cpu: Support thread and module level cache topology

Zhao Liu
2024-10-22T13:36:40Z

Allow cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
target/i386/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f1cbcaf9f4ad..3a5b5557f74b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -240,9 +240,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
uint32_t num_ids = 0;

switch (share_level) {
+ case CPU_TOPOLOGY_LEVEL_THREAD:
+ num_ids = 1;
+ break;
case CPU_TOPOLOGY_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
+ case CPU_TOPOLOGY_LEVEL_MODULE:
+ num_ids = 1 << apicid_module_offset(topo_info);
+ break;
case CPU_TOPOLOGY_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
@@ -250,10 +256,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
num_ids = 1 << apicid_pkg_offset(topo_info);
break;
default:
- /*
- * Currently there is no use case for THREAD and MODULE, so use
- * assert directly to facilitate debugging.
- */
g_assert_not_reached();
}

--
2.34.1