[PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level

Zhao Liu
2024-10-22T13:36:13Z

In the follow-up change, the CPU topology enumeration will be moved to
QAPI. And considerring "invalid" should not be exposed to QAPI as an
unsettable item, so, as a preparation for future changes, remove
"invalid" level from the current CPU topology enumeration structure
and define it by a macro instead.

Due to the removal of the enumeration of "invalid", bit 0 of
CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
level, but will start at the SMT level. Therefore, to honor this change,
update the encoding rule for CPUID[0x1F].

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Tested by the following cases to ensure 0x1f's behavior hasn't
changed:
-smp cpus=24,sockets=2,dies=3,modules=2,cores=2,threads=1
-smp cpus=24,sockets=2,dies=1,modules=3,cores=2,threads=2
-smp cpus=24,sockets=2,modules=3,cores=2,threads=2
-smp cpus=24,sockets=2,dies=3,modules=1,cores=2,threads=2
-smp cpus=24,sockets=2,dies=3,cores=2,threads=2
---
Changes since Patch v3:
* Now commit to stop exposing "invalid" enumeration in QAPI. (Daniel)
---
include/hw/i386/topology.h | 3 ++-
target/i386/cpu.c | 13 ++++++++-----
2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index dff49fce1154..48b43edc5a90 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;

+#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
+
/*
* CPUTopoLevel is the general i386 topology hierarchical representation,
* ordered by increasing hierarchical relationship.
@@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo {
* or AMD (CPUID[0x80000026]).
*/
enum CPUTopoLevel {
- CPU_TOPO_LEVEL_INVALID,
CPU_TOPO_LEVEL_SMT,
CPU_TOPO_LEVEL_CORE,
CPU_TOPO_LEVEL_MODULE,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1ff1af032eaa..638de9c29c4c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -367,20 +367,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = env_archcpu(env);
- unsigned long level, next_level;
+ unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level;

- assert(count + 1 < CPU_TOPO_LEVEL_MAX);
+ assert(count <= CPU_TOPO_LEVEL_PACKAGE);

/*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
- * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1).
+ * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT).
*/
- level = CPU_TOPO_LEVEL_INVALID;
+ level = CPU_TOPO_LEVEL_SMT;
+ base_level = level;
for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo,
CPU_TOPO_LEVEL_PACKAGE,
- level + 1);
+ base_level);

/*
* CPUID[0x1f] doesn't explicitly encode the package level,
@@ -391,6 +392,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
level = CPU_TOPO_LEVEL_INVALID;
break;
}
+ /* Search the next level. */
+ base_level = level + 1;
}

if (level == CPU_TOPO_LEVEL_INVALID) {
--
2.34.1