[PATCH 0/2] KVM: nVMX: Fix an SVI update bug with passthrough APIC

Sean Christopherson
2024-11-01T19:21:16Z

Defer updating SVI (i.e. the VMCS's highest ISR cache) when L2 is active,
but L1 has not enabled virtual interrupt delivery for L2, as an EOI that
is emulated _by KVM_ in such a case acts on L1's ISR, i.e. vmcs01 needs to
reflect the updated ISR when L1 is next run.

Note, L1's ISR is also effectively L2's ISR in such a setup, but because
virtual interrupt deliver is disable for L2, there's no need to update
SVI in vmcs02, because it will never be used.

Chao Gao (1):
KVM: nVMX: Defer SVI update to vmcs01 on EOI when L2 is active w/o VID

Sean Christopherson (1):
KVM: x86: Plumb in the vCPU to kvm_x86_ops.hwapic_isr_update()

arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/kvm/lapic.c | 22 ++++++++++++++++------
arch/x86/kvm/lapic.h | 1 +
arch/x86/kvm/vmx/nested.c | 5 +++++
arch/x86/kvm/vmx/vmx.c | 19 ++++++++++++++++++-
arch/x86/kvm/vmx/vmx.h | 1 +
arch/x86/kvm/vmx/x86_ops.h | 2 +-
7 files changed, 43 insertions(+), 9 deletions(-)

base-commit: e466901b947d529f7b091a3b00b19d2bdee206ee
--
2.47.0.163.g1226f6d8fa-goog