From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "seanjc@google.com" <seanjc@google.com>,
"Gao, Chao" <chao.gao@intel.com>
Cc: "Yang, Weijiang" <weijiang.yang@intel.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"x86@kernel.org" <x86@kernel.org>, "bp@alien8.de" <bp@alien8.de>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"john.allen@amd.com" <john.allen@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"minipli@grsecurity.net" <minipli@grsecurity.net>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"xin@zytor.com" <xin@zytor.com>,
"mlevitsk@redhat.com" <mlevitsk@redhat.com>
Subject: Re: [PATCH v12 15/24] KVM: VMX: Emulate read and write to CET MSRs
Date: Tue, 19 Aug 2025 17:19:42 +0000 [thread overview]
Message-ID: <a06cef50bff3ac618ec4feaa501d416f9841c7a1.camel@intel.com> (raw)
In-Reply-To: <aKShs0btGwLtYlVc@google.com>
On Tue, 2025-08-19 at 09:09 -0700, Sean Christopherson wrote:
> This emulation is wrong (in no small part because the architecture sucks). From
> the SDM:
>
> If the processor does not support Intel 64 architecture, these fields have only
> 32 bits; bits 63:32 of the MSRs are reserved.
>
> On processors that support Intel 64 architecture this value cannot represent a
> non-canonical address.
>
> In protected mode, only 31:0 are loaded.
>
> That means KVM needs to drop bits 63:32 if the vCPU doesn't have LM or if the vCPU
> isn't in 64-bit mode. The last one is especially frustrating, because software
> can still get a 64-bit value into the MSRs while running in protected, e.g. by
> switching to 64-bit mode, doing WRMSRs, then switching back to 32-bit mode.
>
> But, there's probably no point in actually trying to correctly emulate/virtualize
> the Protected Mode behavior, because the MSRs can be written via XRSTOR, and to
> close that hole KVM would need to trap-and-emulate XRSTOR. No thanks.
>
> Unless someone has a better idea, I'm inclined to take an erratum for this, i.e.
> just sweep it under the rug.
Sounds ok to me. All I could think would be something like use the CR/EFER
interceptions and just exit to userspace if (CR0.PE && !EFER.LM && CR4.CET). But
this would require some rototilling and then likely remain un-exercised. Not
sure it's worth it.
next prev parent reply other threads:[~2025-08-19 17:20 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 2:55 [PATCH v12 00/24] Enable CET Virtualization Chao Gao
2025-08-12 2:55 ` [PATCH v12 01/24] KVM: x86: Rename kvm_{g,s}et_msr()* to show that they emulate guest accesses Chao Gao
2025-09-01 7:07 ` Xiaoyao Li
2025-09-02 14:28 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 02/24] KVM: x86: Use double-underscore read/write MSR helpers as appropriate Chao Gao
2025-08-12 2:55 ` [PATCH v12 03/24] KVM: x86: Add kvm_msr_{read,write}() helpers Chao Gao
2025-08-12 2:55 ` [PATCH v12 04/24] KVM: x86: Manually clear MPX state only on INIT Chao Gao
2025-08-12 2:55 ` [PATCH v12 05/24] KVM: x86: Zero XSTATE components on INIT by iterating over supported features Chao Gao
2025-08-12 2:55 ` [PATCH v12 06/24] KVM: x86: Introduce KVM_{G,S}ET_ONE_REG uAPIs support Chao Gao
2025-08-19 17:37 ` Sean Christopherson
2025-08-20 8:28 ` Chao Gao
2025-08-21 13:20 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 07/24] KVM: x86: Report XSS as to-be-saved if there are supported features Chao Gao
2025-08-12 2:55 ` [PATCH v12 08/24] KVM: x86: Refresh CPUID on write to guest MSR_IA32_XSS Chao Gao
2025-08-12 2:55 ` [PATCH v12 09/24] KVM: x86: Initialize kvm_caps.supported_xss Chao Gao
2025-08-12 2:55 ` [PATCH v12 10/24] KVM: x86: Load guest FPU state when access XSAVE-managed MSRs Chao Gao
2025-08-12 2:55 ` [PATCH v12 11/24] KVM: x86: Add fault checks for guest CR4.CET setting Chao Gao
2025-08-12 2:55 ` [PATCH v12 12/24] KVM: x86: Report KVM supported CET MSRs as to-be-saved Chao Gao
2025-08-12 2:55 ` [PATCH v12 13/24] KVM: VMX: Introduce CET VMCS fields and control bits Chao Gao
2025-08-12 2:55 ` [PATCH v12 14/24] KVM: x86: Enable guest SSP read/write interface with new uAPIs Chao Gao
2025-08-12 2:55 ` [PATCH v12 15/24] KVM: VMX: Emulate read and write to CET MSRs Chao Gao
2025-08-19 16:09 ` Sean Christopherson
2025-08-19 17:19 ` Edgecombe, Rick P [this message]
2025-08-19 17:50 ` Sean Christopherson
2025-08-19 17:53 ` Xin Li
2025-08-19 18:35 ` Sean Christopherson
2025-08-20 2:32 ` Chao Gao
2025-08-20 14:12 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 16/24] KVM: x86: Save and reload SSP to/from SMRAM Chao Gao
2025-08-12 2:55 ` [PATCH v12 17/24] KVM: VMX: Set up interception for CET MSRs Chao Gao
2025-08-19 16:11 ` Sean Christopherson
2025-08-19 18:05 ` Xin Li
2025-08-19 18:45 ` Sean Christopherson
2025-08-20 2:10 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 18/24] KVM: VMX: Set host constant supervisor states to VMCS fields Chao Gao
2025-08-18 7:57 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 19/24] KVM: x86: Don't emulate instructions guarded by CET Chao Gao
2025-08-12 2:55 ` [PATCH v12 20/24] KVM: x86: Enable CET virtualization for VMX and advertise to userspace Chao Gao
2025-08-19 18:49 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 21/24] KVM: nVMX: Virtualize NO_HW_ERROR_CODE_CC for L1 event injection to L2 Chao Gao
2025-08-12 2:55 ` [PATCH v12 22/24] KVM: nVMX: Enable CET support for nested guest Chao Gao
2025-08-15 14:24 ` Chao Gao
2025-08-19 17:18 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 23/24] KVM: nVMX: Add consistency checks for CR0.WP and CR4.CET Chao Gao
2025-08-19 17:27 ` Sean Christopherson
2025-08-20 7:29 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 24/24] KVM: nVMX: Add consistency checks for CET states Chao Gao
2025-08-15 22:57 ` [PATCH v12 00/24] Enable CET Virtualization Edgecombe, Rick P
2025-08-18 7:53 ` Chao Gao
2025-08-18 22:25 ` Xin Li
2025-08-19 23:11 ` Sean Christopherson
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