Re: [PATCH v2 2/3] KVM: riscv: selftests: Decode stval to identify exact exception type

Atish Patra
2025-04-30T07:21:03Z

On 4/30/25 12:09 AM, Andrew Jones wrote:
> On Tue, Apr 29, 2025 at 05:18:46PM -0700, Atish Patra wrote:
>> Currently, the sbi_pmu_test continues if the exception type is illegal
>> instruction because access to hpmcounter will generate that. However
>> illegal instruction exception may occur due to the other reasons
>> which should result in test assertion.
>>
>> Use the stval to decode the exact type of instructions and which csrs are
>> being accessed if it is csr access instructions. Assert in all cases
>> except if it is a csr access instructions that access valid PMU related
>> registers.
>>
>> Reviewed-by: Anup Patel <anup@brainfault.org>
>> Signed-off-by: Atish Patra <atishp@rivosinc.com>
>> ---
>> .../testing/selftests/kvm/include/riscv/processor.h | 13 +++++++++++++
>> tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 20 ++++++++++++++++++++
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
>> index 1b5aef87de0f..162f303d9daa 100644
>> --- a/tools/testing/selftests/kvm/include/riscv/processor.h
>> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
>> @@ -11,6 +11,19 @@
>> #include <asm/csr.h>
>> #include "kvm_util.h"
>>
>> +#define INSN_OPCODE_MASK 0x007c
>> +#define INSN_OPCODE_SHIFT 2
>> +#define INSN_OPCODE_SYSTEM 28
>> +
>> +#define INSN_MASK_FUNCT3 0x7000
>> +#define INSN_SHIFT_FUNCT3 12
>> +
>> +#define INSN_CSR_MASK 0xfff00000
>> +#define INSN_CSR_SHIFT 20
>> +
>> +#define GET_RM(insn) (((insn) & INSN_MASK_FUNCT3) >> INSN_SHIFT_FUNCT3)
>> +#define GET_CSR_NUM(insn) (((insn) & INSN_CSR_MASK) >> INSN_CSR_SHIFT)
>> +
>> static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
>> uint64_t idx, uint64_t size)
>> {
>> diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
>> index 6e66833e5941..3c47268df262 100644
>> --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
>> +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
>> @@ -130,9 +130,29 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags)
>>
>> static void guest_illegal_exception_handler(struct pt_regs *regs)
>> {
>> + unsigned long insn;
>> + int opcode, csr_num, funct3;
>> +
>> __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL,
>> "Unexpected exception handler %lx\n", regs->cause);
>>
>> + insn = regs->badaddr;
>> + opcode = (insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT;
>> + __GUEST_ASSERT(opcode == INSN_OPCODE_SYSTEM,
>> + "Unexpected instruction with opcode 0x%x insn 0x%lx\n", opcode, insn);
>> +
>> + csr_num = GET_CSR_NUM(insn);
>> + funct3 = GET_RM(insn);
>> + /* Validate if it is a CSR read/write operation */
>> + __GUEST_ASSERT(funct3 <= 7 && (funct3 != 0 && funct3 != 4),
>> + "Unexpected system opcode with funct3 0x%x csr_num 0x%x\n",
>> + funct3, csr_num);
>> +
>> + /* Validate if it is a HPMCOUNTER CSR operation */
>> + __GUEST_ASSERT((csr_num >= CSR_CYCLE && csr_num <= CSR_HPMCOUNTER31) ||
>> + (csr_num >= CSR_CYCLEH && csr_num <= CSR_HPMCOUNTER31H),
> We should never get csr accesses to the rv32 high registers since we only
> support 64-bit.

Sure. I will remove that along with CSR_CYCLEH in pmu_csr_read_num.

>> + "Unexpected csr_num 0x%x\n", csr_num);
>> +
>> illegal_handler_invoked = true;
>> /* skip the trapping instruction */
>> regs->epc += 4;
>>
>> --
>> 2.43.0
>>
> Otherwise,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>