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Message-ID: <a77e6ccf-e694-b71d-b4e6-fa851459382c@gmail.com>
Date:   Fri, 10 Jun 2022 12:56:38 +0800
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Subject: Re: [kvm-unit-tests PATCH 3/3] x86: Skip perf related tests when pmu
 is disabled
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To:     Jim Mattson <jmattson@google.com>,
        "Yang, Weijiang" <weijiang.yang@intel.com>
Cc:     kvm@vger.kernel.org,
        "Paolo Bonzini - Distinguished Engineer (kernel-recipes.org) (KVM HoF)" 
        <pbonzini@redhat.com>
References: <20220609083916.36658-1-weijiang.yang@intel.com>
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 <587f8bc5-76fc-6cd7-d3d7-3a712c3f1274@gmail.com>
 <987d8a3d-19ef-094d-5c0e-007133362c30@intel.com>
 <CALMp9eT4JD-jTwOmpsayqZvheh4BvWB2aUiRAGsxNT145En6xg@mail.gmail.com>
 <ddff538b-81c4-6d96-bda8-6f614f1304fa@gmail.com>
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 <CALMp9eRO0K7L=OtoE4MWok6_7cy0DX5FyjPw6Sv83cZBCws0AQ@mail.gmail.com>
From:   Like Xu <like.xu.linux@gmail.com>
In-Reply-To: <CALMp9eRO0K7L=OtoE4MWok6_7cy0DX5FyjPw6Sv83cZBCws0AQ@mail.gmail.com>
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On 10/6/2022 12:22 pm, Jim Mattson wrote:
> On Thu, Jun 9, 2022 at 9:16 PM Jim Mattson <jmattson@google.com> wrote:
>>
>> On Thu, Jun 9, 2022 at 7:49 PM Like Xu <like.xu.linux@gmail.com> wrote:
>>
>>> RDPMC Intel Operation:
> 
> Actually, the key phrase is also present in the pseudocode you quoted:
> 
>>> MSCB = Most Significant Counter Bit (* Model-specific *)
>>> IF (((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0)) and (ECX indicates a supported
>>> counter))
>   ...
> 
> The final conjunct in that condition is false under KVM when
> !enable_pmu, because there are no supported counters.

Uh, I have lifted a stone and smashed my own feet.

Please move on with #GP expectation.