Re: [RESEND kvm-unit-tests 1/3] arm: gic: Write one bit per time in gic_irq_set_clr_enable()

[Eric Auger <eric.auger@redhat.com>]

Hi Shaoqin,

On 3/2/23 04:02, Shaoqin Huang wrote:
> When use gic_irq_set_clr_enable() to disable an interrupt, it will
> disable all interrupt since it first read from Interrupt Clear-Enable
> Registers and then write this value with a mask back.

nit: it first read from Interrupt Clear-Enable Registers where '1' indicates that forwarding of the corresponding interrupt is enabled

>
> So diretly write one bit per time to enable or disable interrupt.
directly
> Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper")
> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eirc
> ---
>  lib/arm/gic.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> index 1bfcfcf..89a15fe 100644
> --- a/lib/arm/gic.c
> +++ b/lib/arm/gic.c
> @@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest)
>  void gic_irq_set_clr_enable(int irq, bool enable)
>  {
>  	u32 offset, split = 32, shift = (irq % 32);
> -	u32 reg, mask = BIT(shift);
>  	void *base;
>  
>  	assert(irq < 1020);
> @@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable)
>  		assert(0);
>  	}
>  	base += offset + (irq / split) * 4;
> -	reg = readl(base);
> -	writel(reg | mask, base);
> +	writel(BIT(shift), base);
>  }
>  
>  enum gic_irq_state gic_irq_state(int irq)