[RESEND kvm-unit-tests 0/3] arm: Use gic_enable/disable_irq() macro to clean up code

[RESEND kvm-unit-tests 0/3] arm: Use gic_enable/disable_irq() macro to clean up code

[Shaoqin Huang]

Some tests still use their own code to enable/disable irq, use
gic_enable/disable_irq() to clean up them.

The first patch fixes a problem which will disable all irq when use
gic_disable_irq().

The patch 2-3 clean up the code by using the macro.

Shaoqin Huang (3):
  arm: gic: Write one bit per time in gic_irq_set_clr_enable()
  arm64: timer: Use gic_enable/disable_irq() macro in timer test
  arm64: microbench: Use gic_enable_irq() macro in microbench test

 arm/micro-bench.c | 15 +--------------
 arm/timer.c       | 20 +++-----------------
 lib/arm/gic.c     |  4 +---
 3 files changed, 5 insertions(+), 34 deletions(-)

-- 
2.39.1

[RESEND kvm-unit-tests 1/3] arm: gic: Write one bit per time in gic_irq_set_clr_enable()

[Shaoqin Huang]

When use gic_irq_set_clr_enable() to disable an interrupt, it will
disable all interrupt since it first read from Interrupt Clear-Enable
Registers and then write this value with a mask back.

So diretly write one bit per time to enable or disable interrupt.

Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper")
Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
---
 lib/arm/gic.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/lib/arm/gic.c b/lib/arm/gic.c
index 1bfcfcf..89a15fe 100644
--- a/lib/arm/gic.c
+++ b/lib/arm/gic.c
@@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest)
 void gic_irq_set_clr_enable(int irq, bool enable)
 {
 	u32 offset, split = 32, shift = (irq % 32);
-	u32 reg, mask = BIT(shift);
 	void *base;
 
 	assert(irq < 1020);
@@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable)
 		assert(0);
 	}
 	base += offset + (irq / split) * 4;
-	reg = readl(base);
-	writel(reg | mask, base);
+	writel(BIT(shift), base);
 }
 
 enum gic_irq_state gic_irq_state(int irq)
-- 
2.39.1

[RESEND kvm-unit-tests 2/3] arm64: timer: Use gic_enable/disable_irq() macro in timer test

[Shaoqin Huang]

Use gic_enable/disable_irq() to clean up the code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
---
 arm/timer.c | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/arm/timer.c b/arm/timer.c
index c4e7b10..c0a8388 100644
--- a/arm/timer.c
+++ b/arm/timer.c
@@ -14,9 +14,6 @@
 #include <asm/gic.h>
 #include <asm/io.h>
 
-static void *gic_isenabler;
-static void *gic_icenabler;
-
 static bool ptimer_unsupported;
 
 static void ptimer_unsupported_handler(struct pt_regs *regs, unsigned int esr)
@@ -139,12 +136,12 @@ static struct timer_info ptimer_info = {
 
 static void set_timer_irq_enabled(struct timer_info *info, bool enabled)
 {
-	u32 val = 1 << PPI(info->irq);
+	u32 irq = PPI(info->irq);
 
 	if (enabled)
-		writel(val, gic_isenabler);
+		gic_enable_irq(irq);
 	else
-		writel(val, gic_icenabler);
+		gic_disable_irq(irq);
 }
 
 static void irq_handler(struct pt_regs *regs)
@@ -366,17 +363,6 @@ static void test_init(void)
 
 	gic_enable_defaults();
 
-	switch (gic_version()) {
-	case 2:
-		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
-		gic_icenabler = gicv2_dist_base() + GICD_ICENABLER;
-		break;
-	case 3:
-		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
-		gic_icenabler = gicv3_sgi_base() + GICR_ICENABLER0;
-		break;
-	}
-
 	install_irq_handler(EL1H_IRQ, irq_handler);
 	set_timer_irq_enabled(&ptimer_info, true);
 	set_timer_irq_enabled(&vtimer_info, true);
-- 
2.39.1

[RESEND kvm-unit-tests 3/3] arm64: microbench: Use gic_enable_irq() macro in microbench test

[Shaoqin Huang]

Use gic_enable_irq() to clean up code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
---
 arm/micro-bench.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 8436612..090fda6 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -212,24 +212,11 @@ static void lpi_exec(void)
 
 static bool timer_prep(void)
 {
-	void *gic_isenabler;
-
 	gic_enable_defaults();
 	install_irq_handler(EL1H_IRQ, gic_irq_handler);
 	local_irq_enable();
 
-	switch (gic_version()) {
-	case 2:
-		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
-		break;
-	case 3:
-		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
-		break;
-	default:
-		assert_msg(0, "Unreachable");
-	}
-
-	writel(1 << PPI(TIMER_VTIMER_IRQ), gic_isenabler);
+	gic_enable_irq(PPI(TIMER_VTIMER_IRQ));
 	write_sysreg(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
 	isb();
 
-- 
2.39.1

Re: [RESEND kvm-unit-tests 1/3] arm: gic: Write one bit per time in gic_irq_set_clr_enable()

[Eric Auger]

Hi Shaoqin,

On 3/2/23 04:02, Shaoqin Huang wrote:
> When use gic_irq_set_clr_enable() to disable an interrupt, it will
> disable all interrupt since it first read from Interrupt Clear-Enable
> Registers and then write this value with a mask back.

nit: it first read from Interrupt Clear-Enable Registers where '1' indicates that forwarding of the corresponding interrupt is enabled

>
> So diretly write one bit per time to enable or disable interrupt.
directly
> Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper")
> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eirc
> ---
>  lib/arm/gic.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> index 1bfcfcf..89a15fe 100644
> --- a/lib/arm/gic.c
> +++ b/lib/arm/gic.c
> @@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest)
>  void gic_irq_set_clr_enable(int irq, bool enable)
>  {
>  	u32 offset, split = 32, shift = (irq % 32);
> -	u32 reg, mask = BIT(shift);
>  	void *base;
>  
>  	assert(irq < 1020);
> @@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable)
>  		assert(0);
>  	}
>  	base += offset + (irq / split) * 4;
> -	reg = readl(base);
> -	writel(reg | mask, base);
> +	writel(BIT(shift), base);
>  }
>  
>  enum gic_irq_state gic_irq_state(int irq)

Re: [RESEND kvm-unit-tests 2/3] arm64: timer: Use gic_enable/disable_irq() macro in timer test

[Eric Auger]

On 3/2/23 04:02, Shaoqin Huang wrote:
> Use gic_enable/disable_irq() to clean up the code.
> 
> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>


Thanks

Eric

> ---
>  arm/timer.c | 20 +++-----------------
>  1 file changed, 3 insertions(+), 17 deletions(-)
> 
> diff --git a/arm/timer.c b/arm/timer.c
> index c4e7b10..c0a8388 100644
> --- a/arm/timer.c
> +++ b/arm/timer.c
> @@ -14,9 +14,6 @@
>  #include <asm/gic.h>
>  #include <asm/io.h>
>  
> -static void *gic_isenabler;
> -static void *gic_icenabler;
> -
>  static bool ptimer_unsupported;
>  
>  static void ptimer_unsupported_handler(struct pt_regs *regs, unsigned int esr)
> @@ -139,12 +136,12 @@ static struct timer_info ptimer_info = {
>  
>  static void set_timer_irq_enabled(struct timer_info *info, bool enabled)
>  {
> -	u32 val = 1 << PPI(info->irq);
> +	u32 irq = PPI(info->irq);
>  
>  	if (enabled)
> -		writel(val, gic_isenabler);
> +		gic_enable_irq(irq);
>  	else
> -		writel(val, gic_icenabler);
> +		gic_disable_irq(irq);
>  }
>  
>  static void irq_handler(struct pt_regs *regs)
> @@ -366,17 +363,6 @@ static void test_init(void)
>  
>  	gic_enable_defaults();
>  
> -	switch (gic_version()) {
> -	case 2:
> -		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
> -		gic_icenabler = gicv2_dist_base() + GICD_ICENABLER;
> -		break;
> -	case 3:
> -		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
> -		gic_icenabler = gicv3_sgi_base() + GICR_ICENABLER0;
> -		break;
> -	}
> -
>  	install_irq_handler(EL1H_IRQ, irq_handler);
>  	set_timer_irq_enabled(&ptimer_info, true);
>  	set_timer_irq_enabled(&vtimer_info, true);

Re: [RESEND kvm-unit-tests 3/3] arm64: microbench: Use gic_enable_irq() macro in microbench test

[Eric Auger]

Hi Shaoqin,

On 3/2/23 04:02, Shaoqin Huang wrote:
> Use gic_enable_irq() to clean up code.
> 
> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  arm/micro-bench.c | 15 +--------------
>  1 file changed, 1 insertion(+), 14 deletions(-)
> 
> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
> index 8436612..090fda6 100644
> --- a/arm/micro-bench.c
> +++ b/arm/micro-bench.c
> @@ -212,24 +212,11 @@ static void lpi_exec(void)
>  
>  static bool timer_prep(void)
>  {
> -	void *gic_isenabler;
> -
>  	gic_enable_defaults();
>  	install_irq_handler(EL1H_IRQ, gic_irq_handler);
>  	local_irq_enable();
>  
> -	switch (gic_version()) {
> -	case 2:
> -		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
> -		break;
> -	case 3:
> -		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
> -		break;
> -	default:
> -		assert_msg(0, "Unreachable");
> -	}
> -
> -	writel(1 << PPI(TIMER_VTIMER_IRQ), gic_isenabler);
> +	gic_enable_irq(PPI(TIMER_VTIMER_IRQ));
>  	write_sysreg(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
>  	isb();
>  

Re: [RESEND kvm-unit-tests 1/3] arm: gic: Write one bit per time in gic_irq_set_clr_enable()

[Shaoqin Huang]

Hi Eric,

On 3/2/23 16:19, Eric Auger wrote:
> Hi Shaoqin,
> 
> On 3/2/23 04:02, Shaoqin Huang wrote:
>> When use gic_irq_set_clr_enable() to disable an interrupt, it will
>> disable all interrupt since it first read from Interrupt Clear-Enable
>> Registers and then write this value with a mask back.
> 
> nit: it first read from Interrupt Clear-Enable Registers where '1' indicates that forwarding of the corresponding interrupt is enabled
> 

Thanks for your advice.

>>
>> So diretly write one bit per time to enable or disable interrupt.
> directly

I will fix it in v2.

Thanks,

>> Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper")
>> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> 
> Thanks
> 
> Eirc
>> ---
>>   lib/arm/gic.c | 4 +---
>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/lib/arm/gic.c b/lib/arm/gic.c
>> index 1bfcfcf..89a15fe 100644
>> --- a/lib/arm/gic.c
>> +++ b/lib/arm/gic.c
>> @@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest)
>>   void gic_irq_set_clr_enable(int irq, bool enable)
>>   {
>>   	u32 offset, split = 32, shift = (irq % 32);
>> -	u32 reg, mask = BIT(shift);
>>   	void *base;
>>   
>>   	assert(irq < 1020);
>> @@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable)
>>   		assert(0);
>>   	}
>>   	base += offset + (irq / split) * 4;
>> -	reg = readl(base);
>> -	writel(reg | mask, base);
>> +	writel(BIT(shift), base);
>>   }
>>   
>>   enum gic_irq_state gic_irq_state(int irq)
> 

-- 
Shaoqin