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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id f7-20020ac80147000000b003b2957fb45bsm9910169qtg.8.2023.03.02.00.19.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Mar 2023 00:19:39 -0800 (PST) Message-ID: Date: Thu, 2 Mar 2023 09:19:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Reply-To: eric.auger@redhat.com Subject: Re: [RESEND kvm-unit-tests 1/3] arm: gic: Write one bit per time in gic_irq_set_clr_enable() Content-Language: en-US To: Shaoqin Huang , kvmarm@lists.linux.dev Cc: Andrew Jones , "open list:ARM" References: <20230302030238.158796-1-shahuang@redhat.com> <20230302030238.158796-2-shahuang@redhat.com> From: Eric Auger In-Reply-To: <20230302030238.158796-2-shahuang@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Shaoqin, On 3/2/23 04:02, Shaoqin Huang wrote: > When use gic_irq_set_clr_enable() to disable an interrupt, it will > disable all interrupt since it first read from Interrupt Clear-Enable > Registers and then write this value with a mask back. nit: it first read from Interrupt Clear-Enable Registers where '1' indicates that forwarding of the corresponding interrupt is enabled > > So diretly write one bit per time to enable or disable interrupt. directly > Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper") > Signed-off-by: Shaoqin Huang Reviewed-by: Eric Auger Thanks Eirc > --- > lib/arm/gic.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/lib/arm/gic.c b/lib/arm/gic.c > index 1bfcfcf..89a15fe 100644 > --- a/lib/arm/gic.c > +++ b/lib/arm/gic.c > @@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest) > void gic_irq_set_clr_enable(int irq, bool enable) > { > u32 offset, split = 32, shift = (irq % 32); > - u32 reg, mask = BIT(shift); > void *base; > > assert(irq < 1020); > @@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable) > assert(0); > } > base += offset + (irq / split) * 4; > - reg = readl(base); > - writel(reg | mask, base); > + writel(BIT(shift), base); > } > > enum gic_irq_state gic_irq_state(int irq)