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X-CSE-ConnectionGUID: Oowz/ypbT7GpvuYpQvuO1A== X-CSE-MsgGUID: cHowd1ZYSWuioQjLe1s1Ew== X-IronPort-AV: E=McAfee;i="6700,10204,11415"; a="57995098" X-IronPort-AV: E=Sophos;i="6.15,243,1739865600"; d="scan'208";a="57995098" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 01:33:54 -0700 X-CSE-ConnectionGUID: Qcy2UMLbRIaepBdyJ083tw== X-CSE-MsgGUID: CFL9Pbq7TRmRVanh/NT93w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,243,1739865600"; d="scan'208";a="133782755" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2025 01:33:51 -0700 Date: Sun, 27 Apr 2025 16:54:48 +0800 From: Zhao Liu To: Dapeng Mi Cc: Paolo Bonzini , Sean Christopherson , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi Subject: Re: [PATCH 3/3] target/i386: Support VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL Message-ID: References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> <20250324123712.34096-4-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250324123712.34096-4-dapeng1.mi@linux.intel.com> > @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, Instead of modifying SPR's CPU model directly, we should introduce a new version (SapphireRapids-v4), like Skylake-Server-v4 enables "vmx-eptp-switching".