From: Sean Christopherson <seanjc@google.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, tglx@linutronix.de,
mingo@redhat.com, dave.hansen@linux.intel.com,
Thomas.Lendacky@amd.com, nikunj@amd.com, Santosh.Shukla@amd.com,
Vasant.Hegde@amd.com, Suravee.Suthikulpanit@amd.com,
David.Kaplan@amd.com, x86@kernel.org, hpa@zytor.com,
peterz@infradead.org, pbonzini@redhat.com, kvm@vger.kernel.org,
kirill.shutemov@linux.intel.com, huibo.wang@amd.com,
naveen.rao@amd.com, francescolavra.fl@gmail.com
Subject: Re: [PATCH v5 01/20] KVM: x86: Move find_highest_vector() to a common header
Date: Tue, 29 Apr 2025 07:42:28 -0700 [thread overview]
Message-ID: <aBDlVF4qXeUltuju@google.com> (raw)
In-Reply-To: <20250429061004.205839-2-Neeraj.Upadhyay@amd.com>
On Tue, Apr 29, 2025, Neeraj Upadhyay wrote:
> In preparation for using find_highest_vector() in Secure AVIC
> guest APIC driver, move (and rename) find_highest_vector() to
> apic.h.
>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
> ---
> Changes since v4:
> - No change
>
> arch/x86/include/asm/apic.h | 23 +++++++++++++++++++++++
> arch/x86/kvm/lapic.c | 23 +++--------------------
> 2 files changed, 26 insertions(+), 20 deletions(-)
>
> diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
> index 1c136f54651c..c63c2fe8ad13 100644
> --- a/arch/x86/include/asm/apic.h
> +++ b/arch/x86/include/asm/apic.h
> @@ -500,6 +500,29 @@ static inline bool is_vector_pending(unsigned int vector)
> return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector);
> }
>
> +#define MAX_APIC_VECTOR 256
> +#define APIC_VECTORS_PER_REG 32
> +
> +static inline int apic_find_highest_vector(void *bitmap)
> +{
> + unsigned int regno;
> + unsigned int vec;
> + u32 *reg;
> +
> + /*
> + * The registers in the bitmap are 32-bit wide and 16-byte
> + * aligned. State of a vector is stored in a single bit.
> + */
> + for (regno = MAX_APIC_VECTOR / APIC_VECTORS_PER_REG - 1; regno >= 0; regno--) {
> + vec = regno * APIC_VECTORS_PER_REG;
> + reg = bitmap + regno * 16;
> + if (*reg)
> + return __fls(*reg) + vec;
> + }
NAK. The changelog says nothing about rewriting the logic, and I have zero desire
to review or test this for correctness. If someone has requested that the logic be
cleaned up, then do that as a separate patch (or patches) on top, with a changelog
that justifies the change, because to my eyes this isn't an improvement.
I suspect the rewrite is in part due to REG_POS() being a KVM helper that's poorly
named for a global macro. lapic_vector_set_in_irr() already has open coded
versions of REG_POS() and VEC_POS(), just dedup those.
*sigh*
And you created your own versions of those in get_reg_bitmap() and get_vec_bit().
Please slot the below in. And if there is any more code in this series that is
duplicating existing functionality, try to figure out a clean way to share code
instead of open coding yet another version.
--
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 29 Apr 2025 07:30:47 -0700
Subject: [PATCH] x86/apic: KVM: Deduplicate APIC vector => register+bit math
Consolidate KVM's {REG,VEC}_POS() macros and lapic_vector_set_in_irr()'s
open coded equivalent logic in anticipation of the kernel gaining more
usage of vector => reg+bit lookups.
Use lapic_vector_set_in_irr()'s math as using divides for both the bit
number and register offset makes it easier to connect the dots, and for at
least one user, fixup_irqs(), "/ 32 * 0x10" generates ever so slightly
better code with gcc-14 (shaves a whole 3 bytes from the code stream):
((v) >> 5) << 4:
c1 ef 05 shr $0x5,%edi
c1 e7 04 shl $0x4,%edi
81 c7 00 02 00 00 add $0x200,%edi
(v) / 32 * 0x10:
c1 ef 05 shr $0x5,%edi
83 c7 20 add $0x20,%edi
c1 e7 04 shl $0x4,%edi
Keep KVM's tersely named macros as "wrappers" to avoid unnecessary churn
in KVM, and because the shorter names yield more readable code overall in
KVM.
No functional change intended (clang-19 and gcc-14 generate bit-for-bit
identical code for all of kvm.ko).
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/include/asm/apic.h | 7 +++++--
arch/x86/kvm/lapic.h | 4 ++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index c903d358405d..7082826030ba 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -488,11 +488,14 @@ static inline void apic_setup_apic_calls(void) { }
extern void apic_ack_irq(struct irq_data *data);
+#define APIC_VECTOR_TO_BIT_NUMBER(v) ((v) % 32)
+#define APIC_VECTOR_TO_REG_OFFSET(v) ((v) / 32 * 0x10)
+
static inline bool lapic_vector_set_in_irr(unsigned int vector)
{
- u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
+ u32 irr = apic_read(APIC_IRR + APIC_VECTOR_TO_REG_OFFSET(vector));
- return !!(irr & (1U << (vector % 32)));
+ return !!(irr & (1U << APIC_VECTOR_TO_BIT_NUMBER(vector)));
}
static inline bool is_vector_pending(unsigned int vector)
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index e33c969439f7..13a4bc60e292 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -145,8 +145,8 @@ void kvm_lapic_exit(void);
u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
-#define VEC_POS(v) ((v) & (32 - 1))
-#define REG_POS(v) (((v) >> 5) << 4)
+#define VEC_POS(v) APIC_VECTOR_TO_BIT_NUMBER(v)
+#define REG_POS(v) APIC_VECTOR_TO_REG_OFFSET(v)
static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
{
base-commit: 810a8562c8a326765a35e7c2415bd052cca9dd2a
--
next prev parent reply other threads:[~2025-04-29 14:42 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-29 6:09 [PATCH v5 00/20] AMD: Add Secure AVIC Guest Support Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 01/20] KVM: x86: Move find_highest_vector() to a common header Neeraj Upadhyay
2025-04-29 14:42 ` Sean Christopherson [this message]
2025-04-29 18:09 ` Neeraj Upadhyay
2025-05-07 10:38 ` Borislav Petkov
2025-05-07 11:39 ` Neeraj Upadhyay
2025-06-10 6:32 ` Neeraj Upadhyay
2025-06-10 16:12 ` Sean Christopherson
2025-04-29 6:09 ` [PATCH v5 02/20] x86: apic: Move apic_update_irq_cfg() calls to apic_update_vector() Neeraj Upadhyay
2025-05-07 8:08 ` Thomas Gleixner
2025-04-29 6:09 ` [PATCH v5 03/20] x86/apic: Add new driver for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 04/20] x86/apic: Initialize Secure AVIC APIC backing page Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 05/20] x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 06/20] x86/apic: Initialize APIC ID for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 07/20] x86/apic: Add update_vector() callback for apic drivers Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 08/20] x86/apic: Add update_vector() callback for Secure AVIC Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 09/20] x86/apic: Add support to send IPI " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 10/20] x86/apic: Support LAPIC timer " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 11/20] x86/sev: Initialize VGIF for secondary VCPUs " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 12/20] x86/apic: Add support to send NMI IPI " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 13/20] x86/apic: Allow NMI to be injected from hypervisor " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 14/20] x86/sev: Enable NMI support " Neeraj Upadhyay
2025-04-29 6:09 ` [PATCH v5 15/20] x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 16/20] x86/apic: Handle EOI writes for Secure AVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 17/20] x86/apic: Add kexec support for Secure AVIC Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 18/20] x86/apic: Enable Secure AVIC in Control MSR Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 19/20] x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests Neeraj Upadhyay
2025-04-29 6:10 ` [PATCH v5 20/20] x86/sev: Indicate SEV-SNP guest supports Secure AVIC Neeraj Upadhyay
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