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From: Sean Christopherson <seanjc@google.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, tglx@linutronix.de,
	 mingo@redhat.com, dave.hansen@linux.intel.com,
	Thomas.Lendacky@amd.com,  nikunj@amd.com, Santosh.Shukla@amd.com,
	Vasant.Hegde@amd.com,  Suravee.Suthikulpanit@amd.com,
	David.Kaplan@amd.com, x86@kernel.org,  hpa@zytor.com,
	peterz@infradead.org, pbonzini@redhat.com, kvm@vger.kernel.org,
	 kirill.shutemov@linux.intel.com, huibo.wang@amd.com,
	naveen.rao@amd.com,  francescolavra.fl@gmail.com
Subject: Re: [PATCH v5 01/20] KVM: x86: Move find_highest_vector() to a common header
Date: Tue, 10 Jun 2025 09:12:24 -0700	[thread overview]
Message-ID: <aEhZaMuipi2qePHX@google.com> (raw)
In-Reply-To: <cc3df866-9144-42f0-a24c-fbdcedd48315@amd.com>

On Tue, Jun 10, 2025, Neeraj Upadhyay wrote:
> On 4/29/2025 8:12 PM, Sean Christopherson wrote:
> > Please slot the below in.  And if there is any more code in this series that is
> > duplicating existing functionality, try to figure out a clean way to share code
> > instead of open coding yet another version.
> > 
> > --
> > From: Sean Christopherson <seanjc@google.com>
> > Date: Tue, 29 Apr 2025 07:30:47 -0700
> > Subject: [PATCH] x86/apic: KVM: Deduplicate APIC vector => register+bit math
> > 
> > Consolidate KVM's {REG,VEC}_POS() macros and lapic_vector_set_in_irr()'s
> > open coded equivalent logic in anticipation of the kernel gaining more
> > usage of vector => reg+bit lookups.
> > 
> > Use lapic_vector_set_in_irr()'s math as using divides for both the bit
> > number and register offset makes it easier to connect the dots, and for at
> > least one user, fixup_irqs(), "/ 32 * 0x10" generates ever so slightly
> > better code with gcc-14 (shaves a whole 3 bytes from the code stream):
> > 
> > ((v) >> 5) << 4:
> >   c1 ef 05           shr    $0x5,%edi
> >   c1 e7 04           shl    $0x4,%edi
> >   81 c7 00 02 00 00  add    $0x200,%edi
> > 
> > (v) / 32 * 0x10:
> >   c1 ef 05           shr    $0x5,%edi
> >   83 c7 20           add    $0x20,%edi
> >   c1 e7 04           shl    $0x4,%edi
> > 
> > Keep KVM's tersely named macros as "wrappers" to avoid unnecessary churn
> > in KVM, and because the shorter names yield more readable code overall in
> > KVM.
> > 
> > No functional change intended (clang-19 and gcc-14 generate bit-for-bit
> > identical code for all of kvm.ko).
> > 
> 
> With this change, I am observing difference in generated assembly for VEC_POS
> and REG_POS, as KVM code passes vector param with type "int" to these macros.
> Type casting "v" param of APIC_VECTOR_TO_BIT_NUMBER and APIC_VECTOR_TO_REG_OFFSET
> to "unsigned int" in the macro definition restores the original assembly. Can
> you have a look at this once? Below is the updated patch for this. Can you please
> share your feedback on this?

LGTM.

Ideally, KVM would probably pass around an "unsigned int", but some higher level
APIs in KVM use -1 to indicate an invalid vector (e.g. no IRQ pending), and mixing
and matching types would get a little weird and would require a decent amount of
churn.  So casting in the macro where it matters seems like the best option, at
least for now.

Thanks much for taking care of this!

  reply	other threads:[~2025-06-10 16:12 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-29  6:09 [PATCH v5 00/20] AMD: Add Secure AVIC Guest Support Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 01/20] KVM: x86: Move find_highest_vector() to a common header Neeraj Upadhyay
2025-04-29 14:42   ` Sean Christopherson
2025-04-29 18:09     ` Neeraj Upadhyay
2025-05-07 10:38       ` Borislav Petkov
2025-05-07 11:39         ` Neeraj Upadhyay
2025-06-10  6:32     ` Neeraj Upadhyay
2025-06-10 16:12       ` Sean Christopherson [this message]
2025-04-29  6:09 ` [PATCH v5 02/20] x86: apic: Move apic_update_irq_cfg() calls to apic_update_vector() Neeraj Upadhyay
2025-05-07  8:08   ` Thomas Gleixner
2025-04-29  6:09 ` [PATCH v5 03/20] x86/apic: Add new driver for Secure AVIC Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 04/20] x86/apic: Initialize Secure AVIC APIC backing page Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 05/20] x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 06/20] x86/apic: Initialize APIC ID for Secure AVIC Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 07/20] x86/apic: Add update_vector() callback for apic drivers Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 08/20] x86/apic: Add update_vector() callback for Secure AVIC Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 09/20] x86/apic: Add support to send IPI " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 10/20] x86/apic: Support LAPIC timer " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 11/20] x86/sev: Initialize VGIF for secondary VCPUs " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 12/20] x86/apic: Add support to send NMI IPI " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 13/20] x86/apic: Allow NMI to be injected from hypervisor " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 14/20] x86/sev: Enable NMI support " Neeraj Upadhyay
2025-04-29  6:09 ` [PATCH v5 15/20] x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests Neeraj Upadhyay
2025-04-29  6:10 ` [PATCH v5 16/20] x86/apic: Handle EOI writes for Secure AVIC guests Neeraj Upadhyay
2025-04-29  6:10 ` [PATCH v5 17/20] x86/apic: Add kexec support for Secure AVIC Neeraj Upadhyay
2025-04-29  6:10 ` [PATCH v5 18/20] x86/apic: Enable Secure AVIC in Control MSR Neeraj Upadhyay
2025-04-29  6:10 ` [PATCH v5 19/20] x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests Neeraj Upadhyay
2025-04-29  6:10 ` [PATCH v5 20/20] x86/sev: Indicate SEV-SNP guest supports Secure AVIC Neeraj Upadhyay

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