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charset=us-ascii Content-Disposition: inline In-Reply-To: Just want to confirm with the "lines_per_tag" field, which is related about how to handle current "assert(lines_per_tag > 0)": > --- patch prototype start --- > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 7b223642ba..8a17e5ffe9 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2726,6 +2726,66 @@ static const CPUCaches xeon_srf_cache_info = { > }, > }; > > +static const CPUCaches yongfeng_cache_info = { > + .l1d_cache = &(CPUCacheInfo) { > + .type = DATA_CACHE, > + .level = 1, > + .size = 32 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, This fits AMD APM, and is fine. > + .inclusive = false, > + .self_init = true, > + .no_invd_sharing = false, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l1i_cache = &(CPUCacheInfo) { > + .type = INSTRUCTION_CACHE, > + .level = 1, > + .size = 64 * KiB, > + .line_size = 64, > + .associativity = 16, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, Fine, too. > + .inclusive = false, > + .self_init = true, > + .no_invd_sharing = false, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l2_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 2, > + .size = 256 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 512, > + .lines_per_tag = 1, SDM reserves this field: For 0x80000006 ECX: Bits 11-08: Reserved. So I think this field should be 0, to align with "Reserved". In this patch: https://lore.kernel.org/qemu-devel/20250620092734.1576677-9-zhao1.liu@intel.com/ I add an argument (lines_per_tag_supported) in encode_cache_cpuid80000006(), and for the case that lines_per_tag_supported=false, I assert "lines_per_tag == 0" to align with "Reserved". > + .inclusive = true, > + .self_init = true, > + .no_invd_sharing = false, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l3_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 3, > + .size = 8 * MiB, > + .line_size = 64, > + .associativity = 16, > + .partitions = 1, > + .sets = 8192, > + .lines_per_tag = 1, The 0x80000006 EDX is also reserved in SDM. So I think this field should be 0, too. Do you agree? > + .self_init = true, > + .inclusive = true, > + .no_invd_sharing = true, > + .complex_indexing = false, > + .share_level = CPU_TOPOLOGY_LEVEL_DIE, > + }, > +}; > +