From: Chao Gao <chao.gao@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mlevitsk@redhat.com>, <rick.p.edgecombe@intel.com>,
<weijiang.yang@intel.com>, <xin@zytor.com>,
Mathias Krause <minipli@grsecurity.net>,
John Allen <john.allen@amd.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH v12 06/24] KVM: x86: Introduce KVM_{G,S}ET_ONE_REG uAPIs support
Date: Wed, 20 Aug 2025 16:28:53 +0800 [thread overview]
Message-ID: <aKWHRe4qli+GkqHh@intel.com> (raw)
In-Reply-To: <aKS2WKBbZn6U1uqx@google.com>
>> +#define KVM_X86_REG_MSR (1 << 2)
>> +#define KVM_X86_REG_SYNTHETIC (1 << 3)
>> +
>> +struct kvm_x86_reg_id {
>> + __u32 index;
>> + __u8 type;
>> + __u8 rsvd;
>> + __u16 rsvd16;
>> +};
>
>Some feedback from a while back never got addressed[*]. That feedback still
>looks sane/good, so this for the uAPI:
I missed that comment. Below is the diff I end up with. I moved struct
kvm_x86_reg_id to x86.c and added checks for ARCH (i.e., x86) and size.
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
index e72d9e6c1739..bb17b7a85159 100644
--- a/arch/x86/include/uapi/asm/kvm.h
+++ b/arch/x86/include/uapi/asm/kvm.h
@@ -411,15 +411,23 @@ struct kvm_xcrs {
__u64 padding[16];
};
-#define KVM_X86_REG_MSR (1 << 2)
-#define KVM_X86_REG_SYNTHETIC (1 << 3)
-
-struct kvm_x86_reg_id {
- __u32 index;
- __u8 type;
- __u8 rsvd;
- __u16 rsvd16;
-};
+#define KVM_X86_REG_TYPE_MSR 2
+#define KVM_X86_REG_TYPE_SYNTHETIC_MSR 3
+
+#define KVM_x86_REG_TYPE_SIZE(type) \
+{( \
+ __u64 type_size = type; \
+ \
+ type_size |= type == KVM_X86_REG_TYPE_MSR ? KVM_REG_SIZE_U64 : \
+ type == KVM_X86_REG_TYPE_SYNTHETIC_MSR ? KVM_REG_SIZE_U64 :\
+ 0; \
+ type_size; \
+})
+
+#define KVM_X86_REG_ENCODE(type, index) \
+ (KVM_REG_X86 | KVM_X86_REG_TYPE_SIZE(type) | index)
+
+#define KVM_X86_REG_MSR(index) KVM_X86_REG_ENCODE(KVM_X86_REG_TYPE_MSR, index)
#define KVM_SYNC_X86_REGS (1UL << 0)
#define KVM_SYNC_X86_SREGS (1UL << 1)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3bf098a1183a..28e33269c1e9 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5940,6 +5940,15 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
}
}
+struct kvm_x86_reg_id {
+ __u32 index;
+ __u8 type;
+ __u8 rsvd;
+ __u8 rsvd4:4;
+ __u8 size:4;
+ __u8 x86;
+};
+
static int kvm_translate_synthetic_msr(struct kvm_x86_reg_id *reg)
{
return -EINVAL;
@@ -6072,22 +6081,28 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
break;
r = -EINVAL;
+ if ((reg.id & KVM_REG_ARCH_MASK) != KVM_REG_X86)
+ break;
+
id = (struct kvm_x86_reg_id *)®.id;
- if (id->rsvd || id->rsvd16)
+ if (id->rsvd || id->rsvd4)
+ break;
+
+ if (id->type != KVM_X86_REG_TYPE_MSR &&
+ id->type != KVM_X86_REG_TYPE_SYNTHETIC_MSR)
break;
- if (id->type != KVM_X86_REG_MSR &&
- id->type != KVM_X86_REG_SYNTHETIC)
+ if ((reg.id & KVM_REG_SIZE_MASK) != KVM_REG_SIZE_U64)
break;
- if (id->type == KVM_X86_REG_SYNTHETIC) {
+ if (id->type == KVM_X86_REG_TYPE_SYNTHETIC_MSR) {
r = kvm_translate_synthetic_msr(id);
if (r)
break;
}
r = -EINVAL;
- if (id->type != KVM_X86_REG_MSR)
+ if (id->type != KVM_X86_REG_TYPE_MSR)
break;
value = u64_to_user_ptr(reg.addr);
>
>--
>#define KVM_X86_REG_TYPE_MSR 2ull
>
>#define KVM_x86_REG_TYPE_SIZE(type) \
>{( \
> __u64 type_size = type; \
> \
> type_size |= type == KVM_X86_REG_TYPE_MSR ? KVM_REG_SIZE_U64 : \
> type == KVM_X86_REG_TYPE_SYNTHETIC_MSR ? KVM_REG_SIZE_U64 :\
> 0; \
> type_size; \
>})
>
>#define KVM_X86_REG_ENCODE(type, index) \
> (KVM_REG_X86 | KVM_X86_REG_TYPE_SIZE(type) | index)
>
>#define KVM_X86_REG_MSR(index) KVM_X86_REG_ENCODE(KVM_X86_REG_TYPE_MSR, index)
>--
>
>And then the kernel-only struct overlay becomes:
>
>--
>struct kvm_x86_reg_id {
> __u32 index;
> __u8 type;
> __u8 rsvd;
> __u8 rsvd4:4;
> __u8 size:4;
> __u8 x86;
>}
>--
>
>[*] https://lore.kernel.org/all/ZuGpJtEPv1NtdYwM@google.com
next prev parent reply other threads:[~2025-08-20 8:29 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 2:55 [PATCH v12 00/24] Enable CET Virtualization Chao Gao
2025-08-12 2:55 ` [PATCH v12 01/24] KVM: x86: Rename kvm_{g,s}et_msr()* to show that they emulate guest accesses Chao Gao
2025-09-01 7:07 ` Xiaoyao Li
2025-09-02 14:28 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 02/24] KVM: x86: Use double-underscore read/write MSR helpers as appropriate Chao Gao
2025-08-12 2:55 ` [PATCH v12 03/24] KVM: x86: Add kvm_msr_{read,write}() helpers Chao Gao
2025-08-12 2:55 ` [PATCH v12 04/24] KVM: x86: Manually clear MPX state only on INIT Chao Gao
2025-08-12 2:55 ` [PATCH v12 05/24] KVM: x86: Zero XSTATE components on INIT by iterating over supported features Chao Gao
2025-08-12 2:55 ` [PATCH v12 06/24] KVM: x86: Introduce KVM_{G,S}ET_ONE_REG uAPIs support Chao Gao
2025-08-19 17:37 ` Sean Christopherson
2025-08-20 8:28 ` Chao Gao [this message]
2025-08-21 13:20 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 07/24] KVM: x86: Report XSS as to-be-saved if there are supported features Chao Gao
2025-08-12 2:55 ` [PATCH v12 08/24] KVM: x86: Refresh CPUID on write to guest MSR_IA32_XSS Chao Gao
2025-08-12 2:55 ` [PATCH v12 09/24] KVM: x86: Initialize kvm_caps.supported_xss Chao Gao
2025-08-12 2:55 ` [PATCH v12 10/24] KVM: x86: Load guest FPU state when access XSAVE-managed MSRs Chao Gao
2025-08-12 2:55 ` [PATCH v12 11/24] KVM: x86: Add fault checks for guest CR4.CET setting Chao Gao
2025-08-12 2:55 ` [PATCH v12 12/24] KVM: x86: Report KVM supported CET MSRs as to-be-saved Chao Gao
2025-08-12 2:55 ` [PATCH v12 13/24] KVM: VMX: Introduce CET VMCS fields and control bits Chao Gao
2025-08-12 2:55 ` [PATCH v12 14/24] KVM: x86: Enable guest SSP read/write interface with new uAPIs Chao Gao
2025-08-12 2:55 ` [PATCH v12 15/24] KVM: VMX: Emulate read and write to CET MSRs Chao Gao
2025-08-19 16:09 ` Sean Christopherson
2025-08-19 17:19 ` Edgecombe, Rick P
2025-08-19 17:50 ` Sean Christopherson
2025-08-19 17:53 ` Xin Li
2025-08-19 18:35 ` Sean Christopherson
2025-08-20 2:32 ` Chao Gao
2025-08-20 14:12 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 16/24] KVM: x86: Save and reload SSP to/from SMRAM Chao Gao
2025-08-12 2:55 ` [PATCH v12 17/24] KVM: VMX: Set up interception for CET MSRs Chao Gao
2025-08-19 16:11 ` Sean Christopherson
2025-08-19 18:05 ` Xin Li
2025-08-19 18:45 ` Sean Christopherson
2025-08-20 2:10 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 18/24] KVM: VMX: Set host constant supervisor states to VMCS fields Chao Gao
2025-08-18 7:57 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 19/24] KVM: x86: Don't emulate instructions guarded by CET Chao Gao
2025-08-12 2:55 ` [PATCH v12 20/24] KVM: x86: Enable CET virtualization for VMX and advertise to userspace Chao Gao
2025-08-19 18:49 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 21/24] KVM: nVMX: Virtualize NO_HW_ERROR_CODE_CC for L1 event injection to L2 Chao Gao
2025-08-12 2:55 ` [PATCH v12 22/24] KVM: nVMX: Enable CET support for nested guest Chao Gao
2025-08-15 14:24 ` Chao Gao
2025-08-19 17:18 ` Sean Christopherson
2025-08-12 2:55 ` [PATCH v12 23/24] KVM: nVMX: Add consistency checks for CR0.WP and CR4.CET Chao Gao
2025-08-19 17:27 ` Sean Christopherson
2025-08-20 7:29 ` Chao Gao
2025-08-12 2:55 ` [PATCH v12 24/24] KVM: nVMX: Add consistency checks for CET states Chao Gao
2025-08-15 22:57 ` [PATCH v12 00/24] Enable CET Virtualization Edgecombe, Rick P
2025-08-18 7:53 ` Chao Gao
2025-08-18 22:25 ` Xin Li
2025-08-19 23:11 ` Sean Christopherson
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