From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2
Date: Fri, 19 Sep 2025 14:58:14 -0700 [thread overview]
Message-ID: <aM3R9mshUCJgXg9K@linux.dev> (raw)
In-Reply-To: <20250915114451.660351-7-maz@kernel.org>
On Mon, Sep 15, 2025 at 12:44:41PM +0100, Marc Zyngier wrote:
> +static u8 compute_s1_sh(struct s1_walk_info *wi, struct s1_walk_result *wr,
> + u8 attr)
> +{
> + u8 sh;
> +
> + /*
> + * non-52bit and LPA have their basic shareability described in the
> + * descriptor. LPA2 gets it from the corresponding field in TCR,
> + * conveniently recorded in the walk info.
> + */
> + if (!wi->pa52bit || BIT(wi->pgshift) == SZ_64K)
> + sh = FIELD_GET(PTE_SHARED, wr->desc);
nit: s/PTE_SHARED/KVM_PTE_LEAF_ATTR_LO_S1_SH/ makes it a bit more
obvious what field is being used here (even though it was like this
before).
> @@ -798,11 +819,13 @@ static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par,
> !MEMATTR_IS_DEVICE(final_attr))
> final_attr = MEMATTR(NC, NC);
>
> + s2_sh = FIELD_GET(PTE_SHARED, tr->desc);
> +
s/PTE_SHARED/KVM_PTE_LEAF_ATTR_LO_S2_SH/
Thanks,
Oliver
next prev parent reply other threads:[~2025-09-19 21:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 11:44 [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 01/16] KVM: arm64: Add helper computing the state of 52bit PA support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 02/16] KVM: arm64: Account for 52bit when computing maximum OA Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 03/16] KVM: arm64: Compute 52bit TTBR address and alignment Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 04/16] KVM: arm64: Decouple output address from the PT descriptor Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 05/16] KVM: arm64: Pass the walk_info structure to compute_par_s1() Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2 Marc Zyngier
2025-09-19 21:58 ` Oliver Upton [this message]
2025-09-15 11:44 ` [PATCH v2 07/16] KVM: arm64: Populate PAR_EL1 with 52bit addresses Marc Zyngier
2025-09-19 22:00 ` Oliver Upton
2025-09-20 9:27 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 08/16] KVM: arm64: Expand valid block mappings to FEAT_LPA/LPA2 support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 09/16] KVM: arm64: Report faults from S1 walk setup at the expected start level Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 10/16] KVM: arm64: Allow use of S1 PTW for non-NV vcpus Marc Zyngier
2025-09-19 22:27 ` Oliver Upton
2025-09-20 9:24 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 11/16] KVM: arm64: Allow EL1 control registers to be accessed from the CPU state Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 12/16] KVM: arm64: Don't switch MMU on translation from non-NV context Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 13/16] KVM: arm64: Add filtering hook to S1 page table walk Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker Marc Zyngier
2025-09-19 22:31 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 15/16] KVM: arm64: Populate level on S1PTW SEA injection Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels Marc Zyngier
2025-09-19 22:36 ` Oliver Upton
2025-09-19 22:37 ` [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Oliver Upton
2025-09-21 11:00 ` Marc Zyngier
2025-09-21 10:57 ` Marc Zyngier
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