From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker
Date: Fri, 19 Sep 2025 15:31:41 -0700 [thread overview]
Message-ID: <aM3ZzSwdPsrz5wjI@linux.dev> (raw)
In-Reply-To: <20250915114451.660351-15-maz@kernel.org>
On Mon, Sep 15, 2025 at 12:44:49PM +0100, Marc Zyngier wrote:
> Use the filtering hook infrastructure to implement a new walker
> that, for a given VA and an IPA, returns the level of the first
> occurence of this IPA in the walk from that VA.
>
> This will be used to improve our SEA syndrome reporting.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/kvm_nested.h | 2 +
> arch/arm64/kvm/at.c | 65 +++++++++++++++++++++++++++++
> 2 files changed, 67 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h
> index cce0e4cb54484..2be6c3de74e3d 100644
> --- a/arch/arm64/include/asm/kvm_nested.h
> +++ b/arch/arm64/include/asm/kvm_nested.h
> @@ -353,6 +353,8 @@ struct s1_walk_result {
>
> int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
> struct s1_walk_result *wr, u64 va);
> +int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa,
> + int *level);
>
> /* VNCR management */
> int kvm_vcpu_allocate_vncr_tlb(struct kvm_vcpu *vcpu);
> diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
> index c099bab30cb0d..117ce1ff5e767 100644
> --- a/arch/arm64/kvm/at.c
> +++ b/arch/arm64/kvm/at.c
> @@ -1578,3 +1578,68 @@ int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
>
> return 0;
> }
> +
> +struct desc_match {
> + u64 ipa;
> + int level;
> +};
> +
> +static int match_s1_desc(struct s1_walk_context *ctxt, void *priv)
> +{
> + struct desc_match *dm = priv;
> + u64 ipa = dm->ipa;
> +
> + /* Use S1 granule alignment */
> + ipa &= GENMASK(52, ctxt->wi->pgshift);
> +
Bit 51 again
> + /* Not the IPA we're looking for? Continue. */
> + if (ipa != ctxt->table_ipa)
> + return 0;
> +
> + /* Note the level and interrupt the walk */
> + dm->level = ctxt->level;
> + return -EINTR;
> +}
> +
> +int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa, int *level)
> +{
> + struct desc_match dm = {
> + .ipa = ipa,
> + };
> + struct s1_walk_info wi = {
> + .filter = &(struct s1_walk_filter){
> + .fn = match_s1_desc,
> + .priv = &dm,
> + },
> + .regime = TR_EL10,
> + .as_el0 = false,
> + .pan = false,
> + };
> + struct s1_walk_result wr = {};
> + int ret;
> +
> + ret = setup_s1_walk(vcpu, &wi, &wr, va);
> + if (ret)
> + return ret;
> +
> + /* We really expect the S1 MMU to be on here... */
> + if (WARN_ON_ONCE(wr.level == S1_MMU_DISABLED)) {
> + *level = 0;
> + return 0;
> + }
> +
> + /* Walk the guest's PT, looking for a match along the way */
> + ret = walk_s1(vcpu, &wi, &wr, va);
> + switch (ret) {
> + case -EINTR:
> + /* We interrupted the walk on a match, return the level */
> + *level = dm.level;
> + return 0;
> + case 0:
> + /* The walk completed, we failed to find the entry */
> + return -ENOENT;
> + default:
> + /* Any other error... */
> + return ret;
> + }
> +}
> --
> 2.39.2
>
next prev parent reply other threads:[~2025-09-19 22:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 11:44 [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 01/16] KVM: arm64: Add helper computing the state of 52bit PA support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 02/16] KVM: arm64: Account for 52bit when computing maximum OA Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 03/16] KVM: arm64: Compute 52bit TTBR address and alignment Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 04/16] KVM: arm64: Decouple output address from the PT descriptor Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 05/16] KVM: arm64: Pass the walk_info structure to compute_par_s1() Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2 Marc Zyngier
2025-09-19 21:58 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 07/16] KVM: arm64: Populate PAR_EL1 with 52bit addresses Marc Zyngier
2025-09-19 22:00 ` Oliver Upton
2025-09-20 9:27 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 08/16] KVM: arm64: Expand valid block mappings to FEAT_LPA/LPA2 support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 09/16] KVM: arm64: Report faults from S1 walk setup at the expected start level Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 10/16] KVM: arm64: Allow use of S1 PTW for non-NV vcpus Marc Zyngier
2025-09-19 22:27 ` Oliver Upton
2025-09-20 9:24 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 11/16] KVM: arm64: Allow EL1 control registers to be accessed from the CPU state Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 12/16] KVM: arm64: Don't switch MMU on translation from non-NV context Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 13/16] KVM: arm64: Add filtering hook to S1 page table walk Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker Marc Zyngier
2025-09-19 22:31 ` Oliver Upton [this message]
2025-09-15 11:44 ` [PATCH v2 15/16] KVM: arm64: Populate level on S1PTW SEA injection Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels Marc Zyngier
2025-09-19 22:36 ` Oliver Upton
2025-09-19 22:37 ` [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Oliver Upton
2025-09-21 11:00 ` Marc Zyngier
2025-09-21 10:57 ` Marc Zyngier
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