Re: [PATCH v3 1/4] KVM: x86: relax canonical check for some x86 architectural msrs

[Sean Christopherson <seanjc@google.com>]

On Fri, Sep 12, 2025, Jim Mattson wrote:
> On Fri, Aug 23, 2024 at 6:59 AM Sean Christopherson <seanjc@google.com> wrote:
> > Heh, and for MPX, the SDM kinda sorta confirms that LA57 is ignored, though I
> > doubt the author of this section intended their words to be taken this way :-)
> >
> >   WRMSR to BNDCFGS will #GP if any of the reserved bits of BNDCFGS is not zero or
> >   if the base address of the bound directory is not canonical. XRSTOR of BNDCFGU
> >   ignores the reserved bits and does not fault if any is non-zero; similarly, it
> >   ignores the upper bits of the base address of the bound directory and sign-extends
> >   the highest implemented bit of the linear address to guarantee the canonicality
> >   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> >   of this address.
> 
> I don't believe there was ever a CPU that supported both MPX and LA57. :)
> 
> Late to the party, as usual, but my interest was piqued by the failure
> of KVM_SET_NESTED_STATE prior to v6.13 if L1 had CR4.LA57 set, L2 did
> not, and the VMCS12.HOST_GSBASE had a kernel address > 48 bits wide.
> The canonicalization checks for the *host* state in the VMCS were done
> using the guest's CR4.LA57.
> 
> Shouldn't this series have been cc'd to stable?

Yes :-(

That's my fault.  I balked at the size/scope of the changes, but in hindsight
that was a mistake.