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AJvYcCUaUyuu/QzGva2GII4dZwOE0frS/FcEmdxiB/xkd9kXA4jiRaeNbicAvaJkhId5C7tLKcw=@vger.kernel.org X-Gm-Message-State: AOJu0YyQEARmK/HzK1fqubvDmDYhh+IekLEfgcPbMIuunNaOVP0s6A8l w6VeeM5k6VHIiym2uDLBc57yN/2BHz/zegYCjyZh6zPfMolhXBuf7Hf1yzBVzS1XuB3R3wlmmGc jElY/GQ== X-Google-Smtp-Source: AGHT+IGTd+vEjpomX02lg40sIK070BEa7zAMmWaWfSxkGdN0a6rntlPdVM/Flldu5zvnn8HY9gT5KwIkR3I= X-Received: from pjbpl3.prod.google.com ([2002:a17:90b:2683:b0:330:7ff5:e413]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3f84:b0:32d:f352:f75c with SMTP id 98e67ed59e1d1-33097ff63f6mr1575094a91.13.1758245115597; Thu, 18 Sep 2025 18:25:15 -0700 (PDT) Date: Thu, 18 Sep 2025 18:25:14 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250912232319.429659-1-seanjc@google.com> <20250912232319.429659-19-seanjc@google.com> <55ab5774-0fcc-469a-8edc-59512def2bae@intel.com> Message-ID: Subject: Re: [PATCH v15 18/41] KVM: x86: Don't emulate instructions affected by CET features From: Sean Christopherson To: Chao Gao Cc: Xiaoyao Li , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Lendacky , Mathias Krause , John Allen , Rick Edgecombe , Maxim Levitsky , Zhang Yi Z Content-Type: text/plain; charset="us-ascii" On Thu, Sep 18, 2025, Chao Gao wrote: > >> > >> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c > >> index 542d3664afa3..e4be54a677b0 100644 > >> --- a/arch/x86/kvm/emulate.c > >> +++ b/arch/x86/kvm/emulate.c > >> @@ -178,6 +178,8 @@ > >> #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ > >> #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ > >> #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ > >> +#define ShadowStack ((u64)1 << 57) /* Instruction protected by Shadow Stack. */ > >> +#define IndirBrnTrk ((u64)1 << 58) /* Instruction protected by IBT. */ > >> #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) > >> @@ -4068,9 +4070,9 @@ static const struct opcode group4[] = { > >> static const struct opcode group5[] = { > >> F(DstMem | SrcNone | Lock, em_inc), > >> F(DstMem | SrcNone | Lock, em_dec), > >> - I(SrcMem | NearBranch | IsBranch, em_call_near_abs), > >> - I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far), > >> - I(SrcMem | NearBranch | IsBranch, em_jmp_abs), > >> + I(SrcMem | NearBranch | IsBranch | ShadowStack | IndirBrnTrk, em_call_near_abs), > >> + I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack | IndirBrnTrk, em_call_far), > >> + I(SrcMem | NearBranch | IsBranch | IndirBrnTrk, em_jmp_abs), > > > >> I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), > > > >It seems this entry for 'FF 05' (Jump far, absolute indirect) needs to set > >ShadowStack and IndirBrnTrk as well? > > Yes. I just checked the pseudo code of the JMP instruction in SDM vol2. A far > jump to a CONFORMING-CODE-SEGMENT or NONCONFORMING-CODE-SEGMENT is affected by > both shadow stack and IBT, and a far jump to a call gate is affected by IBT. The SHSTK interaction is only a #GP condition though, and it's not _that_ awful to emulation. While somewhat silly, I think it makes sense to reject FAR JMP if its IBT, but implement the SHSTK check. Rejecting a JMP instruction for SHSTK is weird/confusing (though definitely easier).