Re: [PATCH v5 13/24] KVM: arm64: Writethrough trapped PMOVS register

Colton Lewis
2025-12-12T21:06:55Z

Oliver Upton <oupton@kernel.org> writes:

> On Tue, Dec 09, 2025 at 08:51:10PM +0000, Colton Lewis wrote:
>> Because PMOVS remains trapped, it needs to be written through when
>> partitioned to affect PMU hardware when expected.

>> Signed-off-by: Colton Lewis <coltonlewis@google.com>
>> ---
>> arch/arm64/include/asm/arm_pmuv3.h | 10 ++++++++++
>> arch/arm64/kvm/sys_regs.c | 17 ++++++++++++++++-
>> 2 files changed, 26 insertions(+), 1 deletion(-)

>> diff --git a/arch/arm64/include/asm/arm_pmuv3.h
>> b/arch/arm64/include/asm/arm_pmuv3.h
>> index 60600f04b5902..3e25c0313263c 100644
>> --- a/arch/arm64/include/asm/arm_pmuv3.h
>> +++ b/arch/arm64/include/asm/arm_pmuv3.h
>> @@ -140,6 +140,16 @@ static inline u64 read_pmicfiltr(void)
>> return read_sysreg_s(SYS_PMICFILTR_EL0);
>> }

>> +static inline void write_pmovsset(u64 val)
>> +{
>> + write_sysreg(val, pmovsset_el0);
>> +}
>> +
>> +static inline u64 read_pmovsset(void)
>> +{
>> + return read_sysreg(pmovsset_el0);
>> +}
>> +
>> static inline void write_pmovsclr(u64 val)
>> {
>> write_sysreg(val, pmovsclr_el0);
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 2e6d907fa8af2..bee892db9ca8b 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1307,6 +1307,19 @@ static bool access_pminten(struct kvm_vcpu *vcpu,
>> struct sys_reg_params *p,
>> return true;
>> }

>> +static void writethrough_pmovs(struct kvm_vcpu *vcpu, struct
>> sys_reg_params *p, bool set)
>> +{
>> + u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
>> +
>> + if (set) {
>> + __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask));
>> + write_pmovsset(p->regval & mask);
>> + } else {
>> + __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask));
>> + write_pmovsclr(p->regval & mask);
>> + }

> There's only ever a single canonical guest view of a register. Either it
> has
> been loaded onto the CPU or it is in memory, writing the value to two
> different locations is odd. What guarantees the guest context is on the
> CPU currently? And what about preemption?

My thinking here was pmovs is trapped so the "canonical" view is in
memory, but the guest still expects it to have an effect immediately.

Otherwise we would have to wait until the next load before the value
makes it to hardware. Are you okay with that latency? I'm not sure
how well that's going to work. Consider PMEVTYPER as an example. If I
don't write it to hardware immediately, a guest may expect a counter to
start counting as soon as it is written, but if it's only in memory the
counter won't start until the next load.

Echoing discussion on the previous patch, I wasn't aware preemption was
possible while servicing these register writes. I'll figure out how to
account for that.