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AJvYcCUhCnjQ+zubTx3BvYnG1qwfIEwxApN8H8v9V24jg1p80GbGrviOweqXjl0wR9svtOkrHl8=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+XzkObuDoXWBFiU/9cfFyus0/ULLMSLyuSk76X3YXZ5+zNkvJ d4ctQr8fZEQ2rmq3rFx4mJukHwHwqizzAT/AxgabZ4Ozct/qmg3K7xMPDMn3tvk7VmpW1Z4fFVJ 8F7DZdQ== X-Google-Smtp-Source: AGHT+IGP5yQBkU7MFEQikMCxLwFsQce+og4zqXoPQbaLVM9RO0SEYLXD4zIcmH5z8gekwOMGAc50eKwxSU0= X-Received: from pfbjj13.prod.google.com ([2002:a05:6a00:93ad:b0:7b0:bc2e:9595]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:ac85:b0:7e8:450c:61c0 with SMTP id d2e1a72fcca58-7ff66674fb2mr32717579b3a.48.1767053303232; Mon, 29 Dec 2025 16:08:23 -0800 (PST) Date: Mon, 29 Dec 2025 16:08:21 -0800 In-Reply-To: <2sw7xjtjh4ianp2dz7p24cht2v6u55wcdac4xlrxn5vjgqti77@4ohtwtywinmi> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251127013440.3324671-1-yosry.ahmed@linux.dev> <20251127013440.3324671-11-yosry.ahmed@linux.dev> <2sw7xjtjh4ianp2dz7p24cht2v6u55wcdac4xlrxn5vjgqti77@4ohtwtywinmi> Message-ID: Subject: Re: [PATCH v3 10/16] KVM: selftests: Reuse virt mapping functions for nested EPTs From: Sean Christopherson To: Yosry Ahmed Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Tue, Dec 23, 2025, Yosry Ahmed wrote: > On Tue, Dec 23, 2025 at 03:12:09PM -0800, Sean Christopherson wrote: > > On Thu, Nov 27, 2025, Yosry Ahmed wrote: > > > diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h > > > index fb2b2e53d453..62e10b296719 100644 > > > --- a/tools/testing/selftests/kvm/include/x86/processor.h > > > +++ b/tools/testing/selftests/kvm/include/x86/processor.h > > > @@ -1447,6 +1447,7 @@ struct pte_masks { > > > uint64_t dirty; > > > uint64_t huge; > > > uint64_t nx; > > > + uint64_t x; > > > > To be consistent with e.g. writable, call this executable. > > Was trying to be consistent with 'nx' :) > > > > > > uint64_t c; > > > uint64_t s; > > > }; > > > @@ -1464,6 +1465,7 @@ struct kvm_mmu { > > > #define PTE_DIRTY_MASK(mmu) ((mmu)->pte_masks.dirty) > > > #define PTE_HUGE_MASK(mmu) ((mmu)->pte_masks.huge) > > > #define PTE_NX_MASK(mmu) ((mmu)->pte_masks.nx) > > > +#define PTE_X_MASK(mmu) ((mmu)->pte_masks.x) > > > #define PTE_C_MASK(mmu) ((mmu)->pte_masks.c) > > > #define PTE_S_MASK(mmu) ((mmu)->pte_masks.s) > > > > > > @@ -1474,6 +1476,7 @@ struct kvm_mmu { > > > #define pte_dirty(mmu, pte) (!!(*(pte) & PTE_DIRTY_MASK(mmu))) > > > #define pte_huge(mmu, pte) (!!(*(pte) & PTE_HUGE_MASK(mmu))) > > > #define pte_nx(mmu, pte) (!!(*(pte) & PTE_NX_MASK(mmu))) > > > +#define pte_x(mmu, pte) (!!(*(pte) & PTE_X_MASK(mmu))) > > > > And then here to not assume PRESENT == READABLE, just check if the MMU even has > > a PRESENT bit. We may still need changes, e.g. the page table builders actually > > need to verify a PTE is _writable_, not just present, but that's largely an > > orthogonal issue. > > Not sure what you mean? How is the PTE being writable relevant to > assuming PRESENT == READABLE? Only tangentially, I was try to say that if we ever get to a point where selftests support read-only mappings, then the below check won't suffice because walking page tables would get false positives on whether or not an entry is usable, e.g. if a test wants to create a writable mapping and ends up re-using a read-only mapping. The PRESENT == READABLE thing is much more about execute-only mappings (which selftests also don't support, but as you allude to below, don't require new hardware functionality). > > #define is_present_pte(mmu, pte) \ > > (PTE_PRESENT_MASK(mmu) ? \ > > !!(*(pte) & PTE_PRESENT_MASK(mmu)) : \ > > !!(*(pte) & (PTE_READABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu)))) > > and then Intel will introduce VMX_EPT_WRITE_ONLY_BIT :P