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Wed, 21 Jan 2026 14:12:06 -0800 (PST) Date: Wed, 21 Jan 2026 14:12:05 -0800 In-Reply-To: <24665176b1e6b169441c9f6db9b5d02d073377a4.camel@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251121005125.417831-1-rick.p.edgecombe@intel.com> <20251121005125.417831-12-rick.p.edgecombe@intel.com> <24665176b1e6b169441c9f6db9b5d02d073377a4.camel@intel.com> Message-ID: Subject: Re: [PATCH v4 11/16] KVM: TDX: Add x86 ops for external spt cache From: Sean Christopherson To: Rick P Edgecombe Cc: "kvm@vger.kernel.org" , "linux-coco@lists.linux.dev" , Kai Huang , Xiaoyao Li , Dave Hansen , Yan Y Zhao , Binbin Wu , "kas@kernel.org" , "linux-kernel@vger.kernel.org" , "mingo@redhat.com" , "pbonzini@redhat.com" , "tglx@linutronix.de" , Isaku Yamahata , Vishal Annapurve , Chao Gao , "bp@alien8.de" , "x86@kernel.org" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Jan 20, 2026, Rick P Edgecombe wrote: > Sean, really appreciate you taking a look despite being overbooked. >=20 > On Fri, 2026-01-16 at 16:53 -0800, Sean Christopherson wrote: > > NAK.=C2=A0 I kinda sorta get why you did this?=C2=A0 But the pages KVM = uses for page tables > > are KVM's, not to be mixed with PAMT pages. > >=20 > > Eww.=C2=A0 Definitely a hard "no".=C2=A0 In tdp_mmu_alloc_sp_for_split(= ), the allocation > > comes from KVM: > >=20 > > if (mirror) { > > sp->external_spt =3D (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); > > if (!sp->external_spt) { > > free_page((unsigned long)sp->spt); > > kmem_cache_free(mmu_page_header_cache, sp); > > return NULL; > > } > > } >=20 > Ah, this is from the TDX huge pages series. There is a bit of fallout fro= m TDX=20 > /coco's eternal nemesis: stacks of code all being co-designed at once. >=20 > Dave has been directing us recently to focus on only the needs of the cur= rent > series. Now that we can test at each incremental step we don't have the s= ame > problems as before. But of course there is still desire for updated TDX h= uge > pages, etc to help with development of all the other WIP stuff. >=20 > For this design aspect of how the topup caches work for DPAMT, he asked > specifically for the DPAMT patches to *not* consider how TDX huge pages w= ill use > them. >=20 > Now the TDX huge pages coverletter asked you to look at some aspects of t= hat, > and traditionally KVM side has preferred to=C2=A0look at how the code is = all going to > work together. The presentation of this was a bit rushed and confused, bu= t > looking forward, how do you want to do this? >=20 > After the 130 patches ordeal, I'm a bit amenable to Dave's view. What do = you > think? IMO, it's largely irrelevant for this discussion. Bluntly, the code propos= ed here is simply bad. S-EPT hugepage support just makes it worse. The core issue is that the ownership of the pre-allocation cache is split a= cross KVM and the TDX subsystem (and within KVM, between tdx.c and the MMU), whic= h makes it extremely difficult to understand who is responsible for what, which in = turn leads to brittle code, and sets the hugepage series up to fail, e.g. by unn= ecessarily mixing S-EPT page allocation with PAMT maintenance.q That aside, I generally agree with Dave. The only caveat I'll throw in is = that I do think we need to _at least_ consider how things will likely play out w= hen all is said and done, otherwise we'll probably paint ourselves into a corne= r. E.g. we don't need to know exactly how S-EPT hugepage support will interact= with DPAMT, but IMO we do need to be aware that KVM will need to demote pages ou= tside of vCPU context, and thus will need to pre-allocate pages for PAMT without = having a loaded/running vCPU. That knowledge doesn't require active support in th= e DPAMT series, but it most definitely influences design decisions.