Re: [PATCH] KVM: SVM: Propagate Translation Cache Extensions to the guest

Yosry Ahmed
2026-03-06T16:37:39Z

On Fri, Mar 6, 2026 at 8:19 AM Sean Christopherson <seanjc@google.com> wrote:
>
> On Fri, Mar 06, 2026, Yosry Ahmed wrote:
> > From: Venkatesh Srinivas <venkateshs@chromium.org>
> >
> > TCE augments the behavior of TLB invalidating instructions (INVLPG,
> > INVLPGB, and INVPCID) to only invalidate translations for relevant
> > intermediate mappings to the address range, rather than ALL intermdiate
> > translations.
> >
> > The Linux kernel has been setting EFER.TCE if supported by the CPU since
> > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> > as it may improve performance.
> >
> > KVM does not need to do anything to virtualize the feature,
>
> Please back this up with actual analysis.

Something like this?

If a TLB invalidating instruction is not intercepted, it will behave
according to the guest's setting of EFER.TCE as the value will be
loaded on VM-Enter. Otherwise, KVM's emulation may invalidate more TLB
entries, which is perfectly fine as the CPU is allowed to invalidate
more TLB entries that it strictly needs to.

>
> > only advertise it and allow setting EFER.TCE. Passthrough X86_FEATURE_TCE to
>
> Advertise X86_FEATURE_TCE to userspace, not "passthrough xxx to the guest".
> Because that's all KVM
>
> > the guest, and allow the guest to set EFER.TCE if available.
> >
> > Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> > Signed-off-by: Yosry Ahmed <yosry@kernel.org>
> > Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
>
> Your SoB should come last to capture that the chain of hanlding, i.e. this should
> be:

Ack.

>
> Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
> Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> Signed-off-by: Yosry Ahmed <yosry@kernel.org>
>
[..]
> > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> > index 3407deac90bd6..fee1c8cd45973 100644
> > --- a/arch/x86/kvm/svm/svm.c
> > +++ b/arch/x86/kvm/svm/svm.c
> > @@ -5580,6 +5580,9 @@ static __init int svm_hardware_setup(void)
> > if (boot_cpu_has(X86_FEATURE_AUTOIBRS))
> > kvm_enable_efer_bits(EFER_AUTOIBRS);
> >
> > + if (boot_cpu_has(X86_FEATURE_TCE))
> > + kvm_enable_efer_bits(EFER_TCE);
>
> Hrm, I think we should handle all of the kvm_enable_efer_bits() calls that are
> conditioned only on CPU support in common code. While it's highly unlikely Intel
> CPUs will ever support more EFER-based features, if they do, then KVM will
> over-report support since kvm_initialize_cpu_caps() will effectively enable the
> feature, but VMX won't enable the corresponding EFER bit.
>
> I can't think anything that will go sideways if we rely purely on KVM caps, so
> get to something like this as prep work, and then land TCE in common x86?

Will do.