From: "Nutty Liu" <liujingqi@lanxincomputing.com>
To: <zhouquan@iscas.ac.cn>, <anup@brainfault.org>,
<ajones@ventanamicro.com>, <atishp@atishpatra.org>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>
Subject: Re: [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test
Date: Fri, 20 Jun 2025 17:58:13 +0800 [thread overview]
Message-ID: <ad888bc6-33c7-42d3-b5d1-be191dcded0e@lanxincomputing.com> (raw)
In-Reply-To: <3591f5aed544f9026d8375651936e006b57defdb.1750164414.git.zhouquan@iscas.ac.cn>
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Zicbop extension for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index a0b7dabb5040..ebdc34b58bad 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -83,6 +83,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
> @@ -253,6 +254,8 @@ static const char *config_id_to_str(const char *prefix, __u64 id)
> return "KVM_REG_RISCV_CONFIG_REG(isa)";
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> @@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> + KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> @@ -864,6 +868,11 @@ static __u64 zicbom_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
> };
>
> +static __u64 zicbop_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
> +};
> +
> static __u64 zicboz_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
> @@ -1012,6 +1021,8 @@ static __u64 vector_regs[] = {
> .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
> #define SUBLIST_ZICBOM \
> {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
> +#define SUBLIST_ZICBOP \
> + {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
> #define SUBLIST_ZICBOZ \
> {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
> #define SUBLIST_AIA \
> @@ -1130,6 +1141,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> +KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
> @@ -1204,6 +1216,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zfh,
> &config_zfhmin,
> &config_zicbom,
> + &config_zicbop,
> &config_zicboz,
> &config_ziccrse,
> &config_zicntr,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
next prev parent reply other threads:[~2025-06-20 9:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
2025-06-17 13:10 ` [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size zhouquan
2025-06-20 9:36 ` Nutty Liu
2025-06-24 13:45 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM zhouquan
2025-06-20 9:40 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 3/5] RISC-V: KVM: Allow bfloat16 " zhouquan
2025-06-20 9:49 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test zhouquan
2025-06-20 9:58 ` Nutty Liu [this message]
2025-06-24 13:47 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 " zhouquan
2025-06-20 9:58 ` Nutty Liu
2025-06-24 13:47 ` Andrew Jones
2025-07-17 12:04 ` [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest Anup Patel
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