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Tue, 28 Apr 2026 11:10:32 +0000 Date: Tue, 28 Apr 2026 19:10:22 +0800 From: Chao Gao To: Chenyi Qiang CC: , Sean Christopherson , "Jim Mattson" , Paolo Bonzini , "Farrah Chen" Subject: Re: [PATCH] KVM: VMX: Fall back to IRR scan when PIR is empty despite PID.ON being set Message-ID: References: <20260428070349.1633238-1-chenyi.qiang@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260428070349.1633238-1-chenyi.qiang@intel.com> X-ClientProxiedBy: SG2PR06CA0235.apcprd06.prod.outlook.com (2603:1096:4:ac::19) To CH3PR11MB8660.namprd11.prod.outlook.com (2603:10b6:610:1ce::13) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR11MB8660:EE_|SJ2PR11MB7502:EE_ X-MS-Office365-Filtering-Correlation-Id: b608a26d-b6c6-48db-cfb9-08dea516c38d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|18002099003|22082099003|56012099003; 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The sender >performs two individually-atomic operations that are not a single >transaction: > > 1. pi_test_and_set_pir(vector) -- sets the PIR bit > 2. pi_test_and_set_on() -- sets PID.ON > >The following interleaving triggers the bug: > > Sender vCPU (IPI): Target vCPU (1st sync_pir_to_irr): > B1: set PIR[vector] > A1: pi_clear_on() > A2: pi_harvest_pir() -> sees B1 bit > A3: xchg() -> consumes bit, PIR=0 > (1st sync returns correct max_irr) > B2: set PID.ON = 1 > > Target vCPU (2nd sync_pir_to_irr): > C1: pi_test_on() -> TRUE (from B2) > C2: pi_clear_on() -> ON=0 > C3: pi_harvest_pir() -> PIR empty > C4: *max_irr = -1, early return > IRR NOT SCANNED > >The interrupt is not lost (it resides in the IRR from the first sync and >is recovered on the next vcpu_enter_guest() iteration), but the incorrect >max_irr causes a spurious WARNING and a wasted L2 VM-Enter/VM-Exit cycle. > >Fixes: b41f8638b9d3 ("KVM: VMX: Isolate pure loads from atomic XCHG when processing PIR") Just FYI, I asked Copilot to review commit b41f8638b9d3, and it indeed identified this subtle functional change: " Found 1 regression. In arch/x86/kvm/lapic.c::__kvm_apic_update_irr(), the new if (!pending) return false; drops the old behavior of recomputing *max_irr from APIC_IRR on an empty-PIR path. vmx_sync_pir_to_irr() still calls this helper whenever PID.ON is set and then unconditionally passes max_irr to vmx_set_rvi(), so when hardware has already drained PIR into vIRR/APIC_IRR, max_irr stays -1 and KVM clears RVI despite an interrupt still being pending "